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JPS61107758A - ＧａＡｓ集積回路及びその製造方法 - Google Patents

ＧａＡｓ集積回路及びその製造方法

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Publication number
JPS61107758A
JPS61107758A JP59229181A JP22918184A JPS61107758A JP S61107758 A JPS61107758 A JP S61107758A JP 59229181 A JP59229181 A JP 59229181A JP 22918184 A JP22918184 A JP 22918184A JP S61107758 A JPS61107758 A JP S61107758A
Authority
JP
Japan
Prior art keywords
layer
gaas
elements
integrated circuit
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59229181A
Other languages
English (en)
Inventor
Toshio Oshima
利雄 大島
Naoki Yokoyama
直樹 横山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59229181A priority Critical patent/JPS61107758A/ja
Priority to EP85307819A priority patent/EP0180457B1/en
Priority to DE8585307819T priority patent/DE3586525T2/de
Priority to KR1019850008056A priority patent/KR900000585B1/ko
Publication of JPS61107758A publication Critical patent/JPS61107758A/ja
Priority to US07/094,091 priority patent/US4837178A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はに　ａ　Ａｓ等のＩＣの構成要素となる各素子
を絶縁分離するためビニ、素子間部分を分離する構造及
び方法に関する。
従来、　ＧａＡｓデバイスはＦＥＴが主流をしめ、その
構造は半絶縁性基板上にイオン注入法によりチャネル、
ソース、ドレインを形成しているため特別の素子間分離
が不用であった。しかし、近年、２次元電子ガス利用素
子やヘテロ・バイポーラ・トランジスタ（ＨＢＴ）など
ＭＢＥ　（分子線エピタキシャル成長法）を用いるデバ
イスが試作されはじめ、基板が積層構造となったため素
子間を分離する必要が生じている。
〔従来の技術〕
素子間分離には、エツチングにより素子間部分を除去し
てしまうことが行われているが、それによって生じる段
差や素子占有面積の増大など問題点が多い。もうひとつ
の方法はＨＪｐＯなどを注入することにより不活性化を
行い、素子間を絶縁する方法である。しかし、この方法
も熱的不安定性、充分比抵抗が下らない、基板深くまで
不活性化できないなど実用化に問題がある。
さら（：考えられるのは、シリコンＩＣなどで用いられ
るＵ溝やＹ溝と呼ばれる方法で、これは素子の周囲を深
さ方向に除去した後Ｓ　Ｌ　０２などの絶紛物を埋込む
ものである。
第６図に２次元電子ガス利用素子の分離構造の従来例を
示しており、半絶縁性Ｇ　ａＡ　、ｒ基板（図示せず）
上に形成された非ドープ（ｔｂｎｃＬｏｐｔｄ　）　Ｇ
ａＡｓバッファ層４０層上０二項に、ｉ　−ＡＩＧａＡ
ｓ　スペーサ層４６．キャリヤ供給層のｎ　−Ａ　Ｉ　
Ｇ　ａ　Ａ　７層４５．ｒＬ−Ｇ　ａ　Ａ　ｓ層４４．
ゲートの堀込みエツチングの際のストア　／（とｉＺ　
ルＡｌＧａＡｓ層４３　、　ｎ−ＧａＡｙ　：Ｆ　ンタ
クト層４２．ソースまたはドレイン電極のＡｕＧ　ａ　
１Ａｔｔ層４１、素子表面Ｃ；形成された絶縁膜４９．
配線層の７’　ｉ　−Ａ　ｕ層６０　、６１　、６２　
、ゲート電極４７　、４８を有する。ゲート電極４７は
ゲート電極４８より深く堀込んで形成してあり、ゲート
４７の素子はバイアスをかけてない状態では２次元電子
ガス層がスペーサ層４６の下に形成さｒ′Ｌない所謂エ
ンハンスメント型であり、一方ゲート４８の素子はバイ
アスがＣか＼らない状態でも２次元電子ガス層がスペー
サ層４６下に形成されている所謂ディプレッション型で
ある。この例は素子間部分７０　ＹエツチングＣ：よっ
て除去した実施例であり、段差１；よる断線等の問題や
素子占有面積の問題等かある。
一方、上述のび溝やＶ溝の方法で絶縁物を埋込む場合に
は、Ｇ　ａ　Ａ　Ｊの熱膨張係数が８．７±０．１Ｘ１
０−’（１／Ｋ）であるのに対し、Ｓｉｎ、は５〜６　
Ｘ　１０−’（１／ｆｆ）、Ｓ番Ｎは４　Ｘ　１０−’
　（１／Ｋ）であり大きな差違があり、問題が生ずる。
〔発明が解決しようとする問題点〕
本発明は上述の従来の素子間分離の問題である段差や素
子占有面積の増大、熱的不安定性や充分比抵抗が下がら
ない問題、基板深くまで不活性化できない問題、さら（
二はＳｉｎ、等をＵ溝やＶ溝に埋込んだ際Ｃ：ＧａＡｔ
との熱膨張係数の大きな違いのため、後の高温プロセス
時（ニクラックが入るといった問題を解決するものであ
る。
〔問題点を解決するための手段〕
本発明：二おいては、ＧａＡｓ等のＩＣの素子間絶縁分
離をなすため、素子間部分を半絶縁性領域ま　　・；で
深さ方向（ニエッチング等を行って除去し、その後非ド
ープの高抵抗Ｇ　ａＡ　ｓを埋込む。この場合、ｐ形エ
ピタキシャル層、３形工ピタキシヤル層の両方共絶縁分
離することができるし、ｐ形とル形の積層構造も分離で
きる。またル形エピタキシャル層だけならばｐ形Ｇα、
４ＪＦを埋込むことで可能であり、逆も成り立つ。埋込
まれたＧａＡｓは導電形や不純物ａ度？無視すれば同じ
物質といえるから、同じ熱膨張率、格子定数に持つため
、高１熱処理時のストレスが小さいし、エピタキシャル
層の埋込みＧａＡｓとの界面の物理的、電気的特性も良
好である。
さらにＨ注入されたＧａＡｓのごとく熱処理による比抵
抗の低下現象もないし、溝の深さを深くすることにより
絶縁分離の深さをかンより深くできる。また段差も小さ
く集積化Ｃ；も適している。
埋込む材料としてはＧ　ａ　Ａ　ｚの他（二ＡＩＧαＡ
ｒも可能である。Ａ　Ｉ　Ｇ　ａ　Ａ　ｓはバンドギャ
ップがＧ　ａＡ　ｚより広く、比抵抗がＧ　ａＡ　ｚよ
りも高い。
ＧｃＬＡｓやＡ　Ｉ　Ｇ　ａＡ　ｓの埋込み層の成長方
法としてはＭＢＥ　（分子ビームエピタキシ）　、　Ｍ
ＯＣＶＤ　（有機金属を用いた化学蒸着法）、ＬＰＥ（
液相エピタキシ）　、　ＶＰＥ　（気相エピタキシ）な
どが可能である。
〔実施例〕
第１図〜第４図に本発明をヘテロ・バイポーラ°トラン
ジスタの素子分離に連用した実施例を示す。
第１図（二おいて半絶縁性Ｇ　ａ　Ａ　ｓ基板６（二項
次ｎ”ＧａＡｓ層５（膜厚５ｏｏｏｆｆｉｔ　、　３σ
ａＡｚ層４（膜厚３０００Ａ　）　、　ｐ”ＧａＡｓ層
３（膜厚１０００λ）ｙ　ｎＡＩＧａＡｓ層２（膜厚１
５００Ａ　）　、　ｎ”ＧａＡｓ層１（膜厚１ｓｏｏ、
ｊ）％：　ＭＢＥ　＋二より形成する。次Ｃ：、第２図
（二示すように素子間分離領域ｌ二Ｕ溝７をドライエツ
チング又はＡｒヲ用いたイオンミリングによって形成す
る。
次Ｃ；、第３図Ｃ；おいてＵ溝７の部分を非ドープの高
抵抗のＧａＡｓ　１３　によって埋込む。次（二第４図
に示すごとくヘテロ・バイポーラ・トランジスタを形成
する。５のｎ　ＧａＡｓ層はコレクタ引出し抵抗を下げ
るためのナプコレクタとなり、４のｒｂＧａＡｓ層はコ
レクタとして用いられ、３のｐ　ＧａＡｓ層はペース層
となり、２のｎ　Ａ　Ｉ　Ｇ　ａ　Ａ　を層はワイドギ
ャップエミッタとなり、１のｎ　ＧａＡｓ層はエミッタ
のコンタクト抵抗を下げるコンタクト層として用いる。
図において、パターニングされたエミッタコンタクト層
のｎ　ＧａＡｓ層１Ｃニエミツタ電極９が形成され、そ
の直下のｎ　Ａ　Ｉ　Ｇ　ａ　Ａ　ＪＰＰ２Ｏエミッタ
以外の部分はＰ形Ｃ：転換して核部（二ベース電極１０
が形成され、成長層？掘込んで３＋のサブコレクタ層５
を露出してコレクタ電極１１を形成している。
この例では素子間分離のび溝７の幅は１〜５μ扉程度に
形成している。該Ｕ溝を埋めるＧａＡｓ　８はＭＢＥま
たはＮｏ　ＣＶＤによって形成している。
ココでＧａＡｓ１Ｃの熱膨張係数は８．７±ｏ　、１ｘ
　１ｏ−’（ＶＫ）であり、第４図の各層（２〜６）は
これと同じか、きわめて近い熱膨張係数をもつので熱処
理によるクラックの発生がなく、各成長層との界面（ニ
ストレスか作用することもないので素子特性への悪影響
が全くない。本実施例によれば、ワイドギャップエミッ
タの採用による特性、Ｔなわちベースの７　　　ドーピ
ング濃度を高くしてもベースからエミッタへの逆注入が
なく、高いエミッタ注入効率と低いペース抵抗？持つＨ
ＥＴの特性を最大限ζ：生かすことができる。
第５図Ｃ２次元電子ガス利用素子（二本発明を適用した
例を示している。図（二おいて、非ドープのＧ’ａＡｚ
層６０の上（二項（ニスペーサ層のｉ　−ＡＩＧａＡｓ
層３６．キャリア供給層のｎ　−Ａ　Ｉ　Ｇ　ａ　／−
、ｒ層３５　、３−ＧａＡｓ１Ｃ、エツチングストッパ
となるＡ　Ｉ　Ｇ　ａ　Ａ　ｓ層３３　、　ｎ−ＧａＡ
ｓ　ニア　：／タクト層３２　、　ＡｗＧｇ／Ａｗのソ
ースまたはドレイン電極６１．保護絶縁膜６９．Ｔｉ−
Ａ　ｗの配線層５０，５１．５２が備えられている。そ
してエンハンスメント型素子を構成するゲート電極３７
が深い堀込みシニ形成され、ディプレッンヨン型の素子
を構成するゲート電極６８が浅い堀込み（ストッパ層６
６の深さ）（二形成されている。そして、本発明の適用
により、素子間部分を半絶縁性領域（非ドープＧ　ａ　
Ａ　ｓＰ６Ｏ）まで深さ方向（二二ツｔング？行い除去
した後、非ドープのＧｃＬＡ、ｒ８０を埋込んで絶縁分
離を行っている。
〔発明の効果〕゛゛□ 本発明【：よれば、ＧａＡｓｌＣの素子間部分を半絶縁
性領域まで深さ方向Ｃニエッチング等で除去した後、非
ドープＧ　ａＡ　ｓ又はＧ　ａ　Ａ　Ｉ　Ａ　ｚ等を埋
込むこと（二より、ＧａＡｓ１Ｃの素子間（畷ヨぼ同じ
熱膨張率、格子定数を持つ高抵抗な分離領域を形成する
ことができる。従って、高温熱処理時のストレスが小さ
く、素子と埋込まれた分離領域との界面の物理的、電気
的特性も良好（二なる。さら（二、従来のＨ＋注入され
たＧ　ａＡ　ｚのごとく熱処理による比抵抗の低下もｒ
ｘ　＜　、溝の深さを深くすること（二より、絶縁分離
の深さもかなり深くできる。そして、段差も小さいので
本発明は集積化（；も適している。
【図面の簡単な説明】
第１図〜第４図は本発明の一実施例の製造工程による説
明図（断面図）、第５図はｍ本発明の他の実施例の断面
図、第６図は従来の２次元゛嘔子ガス利用素子の断面図
、 １…ル＋ＧａＡｓ層 ２　・・ｎＡｌＧａＡｓ層 ５　・＝　ｐ　ＣｒａＡｚ　ｌ＠ ４−　ｎ　ＧａＡｓ層 ５−−−　ｎ　ＧａＡｓ層 ６・・・半絶縁性Ｇ　ａ　Ａ　ｚ基板 ７・・・Ｕ溝 ８・・・非ドープの高抵抗ＧａＡｓＪ＠９・・・エミッ
タ電極 １０・・・ベース電極 １１・・・コレクタ電極

Claims (2)

    【特許請求の範囲】
  1. （１）素子間部分に、ＧａＡｓまたはＧａＡｌＡｓ埋込
    層を備え、該埋込層は下層に備えられる半絶縁性ＧａＡ
    ｓ領域に接続し、素子間を分離することを特徴とするＧ
    ａＡｓ集積回路。
  2. （２）素子間部分を下層の半絶縁性領域まで深さ方向に
    除去して溝を形成し、その後ＧａＡｓまたはＧａＡｌＡ
    ｓを成長して該溝を埋込み、素子間分離領域を形成する
    ことを特徴とするＧａＡｓ集積回路の製造方法。
JP59229181A 1984-10-31 1984-10-31 ＧａＡｓ集積回路及びその製造方法 Pending JPS61107758A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP59229181A JPS61107758A (ja) 1984-10-31 1984-10-31 ＧａＡｓ集積回路及びその製造方法
EP85307819A EP0180457B1 (en) 1984-10-31 1985-10-29 Semiconductor integrated circuit device and method for producing same
DE8585307819T DE3586525T2 (de) 1984-10-31 1985-10-29 Halbleiteranordnung mit einer integrierten schaltung und verfahren zu deren herstellung.
KR1019850008056A KR900000585B1 (ko) 1984-10-31 1985-10-30 반도체 집적회로 장치 및 그 제조 방법
US07/094,091 US4837178A (en) 1984-10-31 1987-09-04 Method for producing a semiconductor integrated circuit having an improved isolation structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59229181A JPS61107758A (ja) 1984-10-31 1984-10-31 ＧａＡｓ集積回路及びその製造方法

Publications (1)

Publication Number Publication Date
JPS61107758A true JPS61107758A (ja) 1986-05-26

Family

ID=16888064

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Country Status (5)

Country Link
US (1) US4837178A (ja)
EP (1) EP0180457B1 (ja)
JP (1) JPS61107758A (ja)
KR (1) KR900000585B1 (ja)
DE (1) DE3586525T2 (ja)

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JPH01238161A (ja) * 1988-03-18 1989-09-22 Fujitsu Ltd 半導体装置及びその製造方法
US5041393A (en) * 1988-12-28 1991-08-20 At&T Bell Laboratories Fabrication of GaAs integrated circuits
US5276340A (en) * 1989-11-21 1994-01-04 Fujitsu Limited Semiconductor integrated circuit having a reduced side gate effect
EP0437702B1 (en) * 1989-11-21 1998-08-12 Fujitsu Limited Semiconductor integrated circuit of compound semiconductor devices comprising isolation regions and method of making the same
US5844303A (en) * 1991-02-19 1998-12-01 Fujitsu Limited Semiconductor device having improved electronic isolation
DE69219236T2 (de) * 1991-02-19 1997-08-07 Fujitsu Ltd Halbleiteranordnung mit einem mit sauerstoff angereicherten gebiet und deren herstellungsverfahren
US5399900A (en) * 1991-11-04 1995-03-21 Eastman Kodak Company Isolation region in a group III-V semiconductor device and method of making the same
US5385853A (en) * 1992-12-02 1995-01-31 International Business Machines Corporation Method of fabricating a metal oxide semiconductor heterojunction field effect transistor (MOSHFET)
US5376229A (en) * 1993-10-05 1994-12-27 Miller; Jeffrey N. Method of fabrication of adjacent coplanar semiconductor devices
US6087677A (en) * 1997-11-10 2000-07-11 Integrated Silicon Solutions Inc. High density self-aligned antifuse
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Also Published As

Publication number Publication date
KR900000585B1 (ko) 1990-01-31
EP0180457A2 (en) 1986-05-07
EP0180457A3 (en) 1989-06-07
US4837178A (en) 1989-06-06
DE3586525D1 (de) 1992-09-24
DE3586525T2 (de) 1993-01-14
KR860003666A (ko) 1986-05-28
EP0180457B1 (en) 1992-08-19

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