JPS61107585A - Recording and reproducing device - Google Patents

Abstract

PURPOSE:To make the titled device very convenient by writing address data for retrieval at a recording section of a required program on the recorded tape while reproducing the tape using a VTR and carrying out dubbing on another tape using the second VTR. CONSTITUTION:When a recorded video tape, is reproduced by the first VTR10 and a desired program is reproduced if address data for retrieval is inputted from the ten key, the address data for retrieval is edited by an address data inserting/recording device 20 and written in the recording position in the desired program on the video tape which is being reproduced by the first VTR10. Further, address data for retrieval is a track number, or the like. The program reproduced by the first VTR10 and address data for retrieval can be dubbed by the record VTR10 onto another video tape.

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a recording and reproducing device such as a video tape recorder (hereinafter referred to as VTR), and more particularly to a recording and reproducing device that can record information while in the playback mode. .

BACKGROUND OF THE INVENTION There are cases where it is desired to insert and record search data for searching for the address of a track in which a desired program is recorded on a recorded video tape. However, conventional VTRs require a switching operation between the recording mode and the playback mode, and it is not possible to record search data or the like while remaining in the ζ playback mode. Therefore, for example, it is not possible to perform editing operations such as writing search data into a desired program while playing back a recorded videotape.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a recording and reproducing system that allows predetermined data etc. to be recorded on any screen while reproducing a recorded video tape on a VTR.

Structure of the Invention The video signal recording/playback system of the present invention includes a synchronization separation circuit that receives a playback video signal from a VTR that plays back a recorded tape and separates a synchronization signal, and a synchronization separation circuit that separates a synchronization signal from the video signal to be inserted. video signal generation means for adding the synchronization signal obtained by the separation circuit; switching means for outputting the signal from the video signal generation means during the insertion period and outputting the reproduced video signal when not in the insertion period; and means for sending the output of the means to a recording VTR.

EXAMPLE Below, one example of the present invention will be explained with reference to the drawings.

In FIG. 1, the address data insertion/recording device 20 and the controller 40 are each configured in the form of an adapter, and a first VTRIO for playing back a recorded videotape is connected to an input terminal 20a. , a playback video signal including a synchronization signal is input.

The sync 0 separator 20A separates a vertical sync pulse and a horizontal sync pulse from the reproduced video signal and applies these sync pulses to the video signal generator 20B. controller 4
From 0 onwards, a search address data signal input using a numeric keypad or the like is input to the video signal generator 20B, and this search address data signal is converted into a standard format video signal and a synchronization pulse is added. The resulting composite video signal is applied to the terminal 20CI of the video switch 20G.

The first VTR1 is connected to the terminal 20C2 of the video switch 20C.
A reproduced video signal reproduced at 0 is applied.

In response to an instruction from the controller 40, the video switch 20C is switched to send the signal of the terminal 20CI to the output terminal 20C3 only during the insertion period of, for example, 20H to 24H in one field, and the signal is applied to the terminal 20C2 during other periods. The output terminal 20C3 is switched to send the reproduced video signal to the output terminal 20C3.

The signal at the output terminal 20C3 of the video switch 20C is converted into a signal suitable for VTR recording in the video signal output device 20D, and is applied to the first VTRIO.
Recording current is applied to the video head of the RIO to write search data onto the video tape.

When the second VTR 12 is connected to the video signal output device 20D in recording mode, the video signal reproduced by the first VTR and the search address data can be dubbed onto a video tape.

With the above-described configuration, when a recorded videotape is played back by the first VTR 10 and search address data is input from the numeric keypad while a desired program is being played back, this search address data is stored in the address data insertion record. Edited by the device 20, the first VT
Write to the recording position of the desired program on the videotape being played back on the RIO.

Note that the search address data is, for example, a track number. Further, the program reproduced by the first VTRI'o and the search address data can be dubbed onto another videotape by the second VTR 12.

Next, details of the address data insertion and recording device will be explained with reference to FIG. 2 and subsequent drawings.

The reproduced video signal reproduced by the VTR l0 is input to the synchronization separation circuit 21 of the address data insertion/recording device 20, and a composite synchronization signal is output.

The composite synchronization signal is supplied to an integrating circuit 22 and a horizontal drive circuit 23, respectively, and a vertical synchronization signal.

A horizontal synchronization signal is output, and a line switch signal is obtained from the horizontal synchronization signal by the D flip-flop circuit 24.
These three synchronization signals are input to the synchronization signal generator 25. The synchronization signal generator 25 outputs a combo-not synchronization signal that is in phase with the input synchronization signal. The output composite synchronization signal is input to the controller 40 and divided into horizontal and vertical synchronization signals within the controller 40.
A gate pulse of a predetermined period is generated by a counter 41 and a monostable multi-by-break 42, and this gate pulse determines, for example, the position and period of insertion recording of search data, for example, 20H to 24H.

Further, the controller 40 outputs address data, which is a digital signal obtained by processing search address data input from the input numeric keypad 43 by the CPU 44.

Here, the address data and gate pulse are input to the address data insertion and recording device 20, and a synchronization signal synchronized with the reproduced video signal of the VTR 10 is added to this address data, and the same signal as a normal video signal is added to the address data by the video signal generator 25°. A PM modulation circuit 26. adjusts the level and synchronization signal to the waveform and inserts and records this address data signal. Recording amplifier 27, buffer amplifier 28. Recording drive circuit 29
The signal is then converted into a signal for VTR. This signal is VTR
It is input to the rotary transformer (not shown) of l0, and the video head! 1 is supplied with a recording current, and address data is inserted and recorded.

In the above circuit, the recording amplifier 27. buffer 28,
The recording drive 29 is set to be constantly driven. On the other hand, the switch 30 connected to the input terminal of the recording drive 29 is turned on when there is no gate pulse of the monostable multivibrator 42, and the input signal to the recording drive 29 is bypassed to ground, and the gate I is connected to the input terminal of the recording drive 29. When a pulse occurs, the switch 30 is turned off, the input signal to the recording drive 29 becomes valid, and address data is recorded as described above. Therefore, it is not affected by the rise time of a recording amplifier, etc., and even data as short as several hours can be recorded accurately.

In the embodiment shown in FIG. 2, the address data insertion and recording device 20. Each controller 40 can be connected to a commercially available VT'RIO in the form of an adapter. With this configuration, V
TR also has an address data insertion device 20. controller 4
By connecting 0, desired address data can be inserted into the recorded tape.

In the above device, during insertion recording, the VTRI is generated before and after the rise and fall of the gate pulse as shown in Figure 6d.
A pulse-shaped distorted wave occurs in the reproduced video signal obtained from O, and this may be mistakenly processed as a synchronization signal, resulting in synchronization disturbance.

In order to prevent such synchronization disturbances, a circuit shown in FIG. 3 is provided.

A switch 31 provided between the synchronous separation circuit 21 and the horizontal drive 23 receives the switching pulse shown in FIG. Between A
and while it is at low level, it switches to the B side.

The output of the horizontal drive 23 is applied to one input terminal of a phase comparison circuit 33a of a phase-locked loop (hereinafter referred to as PLL) 33, and compared with the output of the PLL 33 applied via a delay circuit 33b. vCO33c oscillates according to the output of phase comparison circuit 33a and outputs a predetermined pulse, and this pulse is frequency-divided by frequency divider circuit 33b, and when switch 31 is on the A side, VTRIO is output from frequency divider circuit 33d. A pulse that is synchronized with the horizontal pulse reproduced from is obtained.

On the other hand, when the switch 31 is switched to the B side, the PLL 33
The output pulse of the PLL 33 is fed back to the phase comparison circuit 33a through the horizontal drive 23, and even if the horizontal pulse from the VTRIO is disturbed, the output of the PLL 33 is maintained at the correct phase of the horizontal synchronizing pulse.

The output of the frequency dividing circuit 33d is combined with a vertical synchronizing signal by a combining circuit 33e to form a combo-not synchronizing signal, which is applied to the counter 41 of the controller 40.

The monostable multi-pipe rake 32 receives a gate pulse from the monostable multivibrator 42 of the controller 40 and generates a pulse longer than the gate pulse so as to cover the period in which noise occurs in the reproduced video signal before and after insertion recording. A switching pulse shown in FIG. 6r is generated.

With the above circuit configuration, until insertion recording is performed,
The output of the monostable multivibrator 32 is low level, the switch 31 is switched to the A side, and the PLL
33 is controlled by a synchronization signal from a recorded tape played by VTR10 to produce a composite synchronization signal.

On the other hand, when insertion recording is performed, the output pulse of the monostable multipipe lake 32 becomes high level due to the gate pulse, and the switch 31 is switched to the terminal B side. As a result, the output pulse of the PLL 33 is applied to the horizontal drive circuit 23, and the horizontal synchronization pulse is applied to the phase comparator circuit 33a1, so that the output pulses of PL and L33 are locked to the correct phase of the horizontal synchronization pulse.

Therefore, even if there is a disturbance in the horizontal synchronization pulse I output from the VTRIO as shown in FIG. 6e, the correct horizontal synchronization pulse with the phase shown in FIG. 4g is output from the PLL 33. This horizontal synchronization is controlled by the controller 40.
The horizontal sync pulse of the signal to be inserted and recorded is also applied to
It becomes undisturbed.

Next, when performing insertion recording in the device shown in Figure 2, signals such as address data to be inserted pass through a filter and are further filtered.
There is a delay of about 2 μs due to MR7A, so when a video tape with insertion recording is played back on a VTR, the horizontal synchronization immediately after the insertion recording period on the playback screen may be disrupted, or the color processing circuit of the VTR may malfunction, causing the same delay immediately after the insertion recording period. A phenomenon that causes color shift in images occurs. This is because the horizontal synchronization between the inserted and recorded signal and the video signal of the other portions causes a phase shift due to the delay of the inserted and recorded signal. Therefore, if the horizontal synchronization of the signal to be inserted and recorded is advanced in advance, such color shift of the image can be prevented.

For this reason, a delay circuit 35 is provided at the horizontal synchronization signal output terminal of the synchronization signal generator 25, and the horizontal synchronization signal (IH-2
A horizontal synchronizing pulse that is apparently advanced by 2 μs is applied to the video signal generator 25. This compensates for the signal delay caused by the filter and I''M modulation as described above, making it possible to reproduce an image without color shift.

As the delay circuit 35, as shown in FIG. 4, a monostable multivibrator 35a is connected to the output of the horizontal drive circuit 23.
, 35b are connected in cascade. In this circuit, the monostable multivibrator 35a generates a pulse shown in FIG. 5 that rises in synchronization with the rise of the output pulse of the horizontal drive 23 and falls after IH-2 μ seconds, and... As a result, the monostable multi-bi break 35b outputs a pulse with a predetermined width, shown in FIG. 5, which is advanced by 2 μs.

Effects of the Invention As described above, according to the present invention, the recorded tape can be
It is extremely convenient to use because it is possible to write search address data, etc. in the recorded portion of a desired program on this tape while playing back on the TR, and it can also be dubbed onto another tape using a second VTR.

[Brief explanation of drawings]

Fig. 1 is a block circuit diagram showing an embodiment of the present invention, Fig. 2 is a detailed circuit diagram of the main parts of the circuit shown in Fig. 1, and Fig. 3 is a detailed circuit diagram of the synchronizing signal generator of the circuit shown in Fig. 2. 4 is a circuit diagram showing a part of the synchronizing signal generator of the circuit in FIG. 2, FIG. 5 is an explanatory diagram of the operation of the circuit in FIG. It is an output waveform diagram of the part shown by a-4. 10 1st VTR, l 2=-2nd VTR. 20 - Address data insertion and recording device, 20A... Synchronization separation device, 20B - Video signal generator, 20C...
Switch, 20D... Video signal output circuit, 40...
controller.

Claims (1)

[Claims] A sync separation circuit that receives a playback video signal from a VTR that plays back a recorded tape and separates a sync signal; and a video signal generation means that adds the sync signal obtained by the sync separation circuit to a video signal to be inserted. , switching means for outputting the signal from the video signal generating means during the insertion period and outputting the reproduced video signal when not in the insertion period, and means for sending the output of the switching means to a recording VTR. A recording/reproducing device characterized by: