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JPS6098652A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6098652A
JPS6098652A JP20696883A JP20696883A JPS6098652A JP S6098652 A JPS6098652 A JP S6098652A JP 20696883 A JP20696883 A JP 20696883A JP 20696883 A JP20696883 A JP 20696883A JP S6098652 A JPS6098652 A JP S6098652A
Authority
JP
Japan
Prior art keywords
semiconductor chip
bonding
pads
package
same signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20696883A
Other languages
Japanese (ja)
Other versions
JPH0216013B2 (en
Inventor
Toshiyuki Ogawa
小川　俊行
Yoichi Hida
洋一 飛田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP20696883A priority Critical patent/JPS6098652A/en
Publication of JPS6098652A publication Critical patent/JPS6098652A/en
Publication of JPH0216013B2 publication Critical patent/JPH0216013B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable optimum wire bonding even in the case of assemblying the same semiconductor chip to different packages, by a method wherein a plurality of bonding pads for the same signal are provided in the semiconductor chip. CONSTITUTION:Assume the signal pads 2 provided to the semiconductor chip 1 are bonding pads 2a-2d, the pads 2a and 2b are the same signal sections, and the pads 2c and 2d are the same signal sections, too. The semiconductor chip can be put in optimum wire bonding to different packages by providing a plurality of the bonding pads for the same signal according to the packages.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、同一の半導体チップを異なるパッケージに
アセン７りする際、より効果的に、かつ、１１）単にワ
イヤボンティングすることができるようにした半導体装
置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides a method for assembling the same semiconductor chip into different packages more effectively and 11) by simply wire bonding. The present invention relates to a semiconductor device.

〔従来技術〕[Prior art]

従来のＩ）　Ｉ　Ｌパッケージの場合、第１図に示すよ
うに、半導体ヂンプ１の中にある信將バッド（ボンディ
ング用バッド）２と、フレーム３の信号を入力したり、
出力したりする（Ｓ　神人出力部４とを、ワイヤボンド
５でｆ＃：［し、半導体チンブ１の信号を外部に取り出
したり取り入れたりしている。In the case of the conventional I)I L package, as shown in Fig. 1, signals from the signal pad (bonding pad) 2 and the frame 3 inside the semiconductor chip 1 are input,
The signal from the semiconductor chip 1 is taken out and taken in to the outside by the wire bond 5.

ＤＩＬパッケージでは、フレーム３は、第１図に示すよ
う九両刀向に２列に伸びている。In the DIL package, the frames 3 extend in two rows in a nine-sided direction, as shown in FIG.

一方、ＺＩＬパンケージでは、第２図に示すよ５　Ｋ　
Ｉ）　Ｉ　Ｌパッケージと異なり、フレーム３は一方向
側に伸びており、フレーム３の轍方向の寸法を短（する
ため、フレーム３の他方向１則に借精入出力部がなく、
フレーム３の、紙面に対して両側および下方にある。し
たがって、最適なボンティング用バッドの位置は、ＤＩ
ＬパッケージとＺＩＬパッケージでは異なったものとな
っている。On the other hand, in the ZIL pancake, 5K is shown in Figure 2.
I) Unlike the I L package, the frame 3 extends in one direction, and in order to shorten the dimension of the frame 3 in the rut direction, there is no borrow output part in the other direction of the frame 3,
They are located on both sides and below the frame 3 relative to the plane of the paper. Therefore, the optimal bonding pad position is DI
The L package and the ZIL package are different.

このようにそれぞれ異なるパッケージにおける従来の半
導体デツプ１では、ボンティング用バッド２は同−信−
号についてはＩ　１１．８１のみであり、例えばＤ　Ｉ
　ＬパンケージとＺＩＩ、パッケージＫ　同一の半導体
チップ１を７センフリする場合、ワイヤボンド用の導線
が長くなるとか、自動機圧対応しにくいなどの欠点があ
った。In this way, in the conventional semiconductor depth 1 in each different package, the bonding pad 2 is
Regarding the issue, there is only I 11.81, for example, D I
L Pancage, ZII, and Package K When reproducing seven identical semiconductor chips 1, there were drawbacks such as the need for long conductors for wire bonding and the difficulty in adapting to automatic machine pressure.

〔発明の４１ｉ＊Ｊ この発明は、上記のような従来のものの欠点を除去する
ためになされたもので、半導体チップ内に同一信号のボ
ンディング用パッドを複数個設けることにより、異なる
パンケージに同一の半導体チップを７セン７′すした場
合でも、最適にワイヤポンドできるよう圧したものであ
る。[41i*J of the Invention This invention was made in order to eliminate the drawbacks of the conventional products as described above. By providing a plurality of bonding pads for the same signal in a semiconductor chip, the same signal can be bonded to different pancages. The pressure is such that even if the semiconductor chip is 7cm thick, it can be wire-pounded optimally.

〔発明の実施例〕[Embodiments of the invention]

第３図、第４図はそれぞれこの発明の一実施例を示すも
ので、それぞれ第１図、第２図に対応するものである。FIGS. 3 and 4 each show an embodiment of the present invention, and correspond to FIGS. 1 and 2, respectively.

すなわち、第３図の実施例はＤＬＬパンケージを示し、
第４図はＺＩＬパッケージを示すものである。That is, the embodiment of FIG. 3 shows a DLL panpackage,
FIG. 4 shows a ZIL package.

第３図、第４図では、半導体チップＩＫ設ける７１バン
ド（ボンティング用バンド）２を第１図。3 and 4, the 71 band (bonting band) 2 provided on the semiconductor chip IK is shown in FIG.

第２図の他に、ホンティング用バンド２ａ、ｌｄとして
設けたものである。いま、半導体チップ１のボンティン
グ用バンドを第３図、第４図のように２　ａ　ｌ　２　
ｂ　ｔ　２　ｃ　ｒ　２　ｄとすると、ボンディング用
パッド２ａと２ｂは同一信号部であり、また、ボンディ
ング用バンド２ｃと２ｄも同一４３号部である。In addition to those shown in FIG. 2, these bands are provided as honting bands 2a and ld. Now, as shown in FIGS. 3 and 4, the bonding band for the semiconductor chip 1 is 2 a l 2.
If b t 2 cr 2 d, the bonding pads 2a and 2b are the same signal section, and the bonding bands 2c and 2d are also the same No. 43 section.

＠３図、第４図のように、同一信号のボンディング用パ
ッド２ａ、２ｂおよび２ｃ、２ｄを、パンケージに応じ
て複数個設けることにより、同一半導体チップ１を異な
るパンケージに最適にワイヤポンドすることができる。As shown in Figures 3 and 4, by providing a plurality of bonding pads 2a, 2b, 2c, and 2d for the same signal depending on the pancage, the same semiconductor chip 1 can be optimally wire bonded to different pancages. I can do it.

すなわち、■）ＩＬパッケージでは、２ｂおよび２ｄを
ボンティング用パッドとして使用し、２ａおよび２ｃは
使用しない。That is, (2) in the IL package, 2b and 2d are used as bonding pads, and 2a and 2c are not used.

また、ＺＩＬパンケージでは、２ａおよび２ｃをポンテ
ィング用パッドとして使用し、２ｂおよび２ｄは使用し
ない。これにより、Ｄｌｌ、バック−ジ、ｚＩＬパンケ
ージとも九同−半導体チンブ１で、最短距離にワイヤボ
ンティングすることができる。Furthermore, in the ZIL pancage, 2a and 2c are used as pads for ponting, and 2b and 2d are not used. As a result, wire bonding can be performed at the shortest distance with the same semiconductor chip 1 for the Dll, back, and zIL pancakes.

なお、上記実施例は、ＤＩＬパッケージ、ＺＩＬパンケ
ージについて説明したが、この発明はこれに限らず、Ｓ
ＩＬパッケージその他、どんなパッケージ九も適用でき
るものである。Note that although the above embodiments have been described with respect to a DIL package and a ZIL package, the present invention is not limited thereto;
Any package other than the IL package can be applied.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明は、半導体チップを谷樋
のパンケージに４用した場合でも最適なワイヤホンティ
ングが０ｊ能なようにパッケージに応じて複数個のボン
ディング用パッドを半導体チップに設けたので、いずれ
のパンケージＫｊＭ用した場合でも、前記ポンティング
用パッドを選択的に使用することによって、最適なワイ
ヤボンティングを実現することができる利点がある。As explained above, the present invention provides a plurality of bonding pads on a semiconductor chip according to the package so that optimal wire bonding can be performed even when the semiconductor chip is used in a 4-way pan cage. Therefore, no matter which pancage KjM is used, optimal wire bonding can be achieved by selectively using the bonding pads.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はＤＩＬパンケージの平面図、第２図はｚＩＩＪ
パッケージの平面図、第３図、第４図はそれぞれＤＩＬ
パッケージ、ＺＩＬパンケージでのこの発明の一実施例
を説明するためのＤＩＬパッケージおよびＺＩＬパンケ
ージの平面図である。 図中、１は半導体チップ、Ｌ　２ａ、２ｂ＋　２ｃ＋２
ｄは信号パッド（ボンディング用バンド）、３はフレー
ム、４は信号入出力部、５はワイヤポンドである。 なお、図中の同一符号は同一または相当部分を示す。 代理人　大岩増雄　（外２名） 第１図 １ 第３図 第４図 手続補正書（自発） １、事件の表示　特願昭　５１１−２０６９１３８号２
　発明の名称　半導体装置 ；３．１市正を４る習 事ｆ’ｌとの関係　″４４゛許出η（ｉ人件　所　東京
都千代１ｔ１区丸の内二丁［”１２　ａ　：３号名　称
　（６０１）三菱電機株式会社 代表者片由仁八部 ４、代理人 ｆｉ　所　東５；【都千代ＩＩ　Ｉ区丸の内二１１１２
番：３シ；５　補ＩＦの対象 明細書の発明のｉｔＴ細な説明のＩＩおよび図面６、補
正の内容 （１）　明細再給２β、１３行〜１４ｑ１の「ホンディ
ング用パッド」を、［ホンディング用パッド２」と補正
する。 （２）同じく第３頁１８行〜１９マ１の「第２図の他に
、ホンディング用パッド２ａ、２ｄとして設けたもので
ある。１を、「第２図に対して、ポンディング用パツＩ
・２ａ、２ｂおよび２ｃ、２ｄとして設けたものである
。」と補１１−する。 （３）　図面ε（”ｔ３図、第４図を別紙のように補Ｉ
Ｆする。 以　１゜Figure 1 is a plan view of the DIL pancage, Figure 2 is the zIIJ
The top view of the package, Figures 3 and 4 are DIL.
FIG. 2 is a plan view of a DIL package and a ZIL pancake for explaining an embodiment of the present invention in a package and a ZIL pancake. In the figure, 1 is a semiconductor chip, L 2a, 2b+ 2c+2
d is a signal pad (bonding band), 3 is a frame, 4 is a signal input/output section, and 5 is a wire pad. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 1 Figure 3 Figure 4 Procedural amendment (voluntary) 1. Indication of case Patent application No. 511-2069138 2
Name of the invention: Semiconductor device; 3.1 Relationship with the city hall training f'l ``44゛ permission η (i Personnel location: 2-chome, Marunouchi, 1t1-ku, Chiyo, Tokyo [''12 a: 3 name ( 601) Mitsubishi Electric Co., Ltd. Representative Katayuni 8be 4, agent fi Location Higashi 5; [Miyakochiyo II I-ku Marunouchi 2 1112
Number: 3 C; 5 ItT Detailed Explanation of the Invention in the Target Specification of Supplementary IF, Drawing 6, Contents of Amendment (1) Specification Resupply 2β, “Honding Pad” in lines 13 to 14q1, [ "Honding pad 2" is corrected. (2) Similarly, page 3, lines 18 to 19, ma 1, ``In addition to Figure 2, pads 2a and 2d are provided for bonding. Pats I
・These are provided as 2a, 2b, 2c, and 2d. ", supplement 11-. (3) Drawing ε ("t3 and 4 as attached)
F. Less than 1゜

Claims (1)

【特許請求の範囲】[Claims] 半導体チップに設けられたポンディング用バンドとフレ
ームに設けられた信号入出力部とをワイヤボンティング
する半導体装置において、前記半導体チップに、この半
導体チップを通用する各種のパンケージに応じて前記ポ
ンディング用バットを選択的に使用するため予め同一信
号のボンディング用バンドを複数個設けたことを特徴と
する半導体装置。In a semiconductor device in which a bonding band provided on a semiconductor chip and a signal input/output section provided on a frame are wire-bonded, the bonding band is attached to the semiconductor chip according to various types of pancages through which the semiconductor chip can pass. 1. A semiconductor device characterized in that a plurality of bonding bands of the same signal are provided in advance in order to selectively use a bonding bat.
JP20696883A 1983-11-02 1983-11-02 Semiconductor device Granted JPS6098652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20696883A JPS6098652A (en) 1983-11-02 1983-11-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20696883A JPS6098652A (en) 1983-11-02 1983-11-02 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6098652A true JPS6098652A (en) 1985-06-01
JPH0216013B2 JPH0216013B2 (en) 1990-04-13

Family

ID=16531982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20696883A Granted JPS6098652A (en) 1983-11-02 1983-11-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6098652A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62114256A (en) * 1985-11-13 1987-05-26 Mitsubishi Electric Corp Semiconductor device
JPS63208235A (en) * 1987-02-24 1988-08-29 Nec Corp Semiconductor device
JPH01107548A (en) * 1987-10-20 1989-04-25 Hitachi Ltd Semiconductor device
US4974053A (en) * 1988-10-06 1990-11-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device for multiple packaging configurations
EP0402592A2 (en) * 1989-06-13 1990-12-19 Kabushiki Kaisha Toshiba Master slice semiconductor device and method of forming it
US4990996A (en) * 1987-12-18 1991-02-05 Zilog, Inc. Bonding pad scheme
JPH03238839A (en) * 1990-02-15 1991-10-24 Nec Corp Semiconductor integrated circuit device
US5905300A (en) * 1994-03-31 1999-05-18 Vlsi Technology, Inc. Reinforced leadframe to substrate attachment
US5965948A (en) * 1995-02-28 1999-10-12 Nec Corporation Semiconductor device having doubled pads

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0635910U (en) * 1992-10-16 1994-05-13 株式会社ニコン Beam injection device
JPH0657572U (en) * 1993-01-14 1994-08-09 レーザーテクノ株式会社 Laser device for marking out
JP7079889B1 (en) 2021-11-30 2022-06-02 株式会社タムラ製作所 Solder alloys, solder joints, solder pastes and semiconductor packages

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5173973U (en) * 1974-12-05 1976-06-10
JPS5456360A (en) * 1977-10-14 1979-05-07 Hitachi Ltd Production of semiconductor chips
JPS5895044U (en) * 1981-12-18 1983-06-28 セイコーインスツルメンツ株式会社 IC chip terminal structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5173973U (en) * 1974-12-05 1976-06-10
JPS5456360A (en) * 1977-10-14 1979-05-07 Hitachi Ltd Production of semiconductor chips
JPS5895044U (en) * 1981-12-18 1983-06-28 セイコーインスツルメンツ株式会社 IC chip terminal structure

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62114256A (en) * 1985-11-13 1987-05-26 Mitsubishi Electric Corp Semiconductor device
JPS63208235A (en) * 1987-02-24 1988-08-29 Nec Corp Semiconductor device
JPH01107548A (en) * 1987-10-20 1989-04-25 Hitachi Ltd Semiconductor device
US4990996A (en) * 1987-12-18 1991-02-05 Zilog, Inc. Bonding pad scheme
US4974053A (en) * 1988-10-06 1990-11-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device for multiple packaging configurations
EP0402592A2 (en) * 1989-06-13 1990-12-19 Kabushiki Kaisha Toshiba Master slice semiconductor device and method of forming it
JPH03238839A (en) * 1990-02-15 1991-10-24 Nec Corp Semiconductor integrated circuit device
US5905300A (en) * 1994-03-31 1999-05-18 Vlsi Technology, Inc. Reinforced leadframe to substrate attachment
US5965948A (en) * 1995-02-28 1999-10-12 Nec Corporation Semiconductor device having doubled pads

Also Published As

Publication number Publication date
JPH0216013B2 (en) 1990-04-13

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