JPS6094759A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the drain capacity of a semiconductor device by controlling a P type silicon substrate, an N-well, the surface of the substrate, P type and N type impurity layers to the specific impurity densities, and forming the N-well, and P type and N type impurity layers to the specific depths. CONSTITUTION:5X10<14>cm<-3> or lower of impurity density is used as a P type silicon substrate 201, and an N-well 202 is formed in depth of 2-10mum, and 1- 10X10<14>cm<-3> of impurity density. An element separation between MOS transistors is performed in a thermally oxidized film 203, and a channel stopper 204 is formed by P type diffused layer. Phosphorus ions are implanted by 1-5X 10<12>cm<-2> in the N-well region, boron ions are implanted to the P type substrate N-channel region, heat treated, and an N type diffused layer 206 and a P type diffused layer 207 are formed to become 0.5-1.5mum of depth, 1-3X10<16>cm<-3> of substrate surface density N-well region and N type substrate regions 1-6X 10<13>cm<-3>. A source and drain diffused layer 208 and a drain diffused layer 205 are formed by implanting ions to the gate electrode 210 of polycrystalline silicon, opening, and the forming wirings 209, thereby forming a passivation film 211.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an 0MO8 semiconductor device, and mainly provides a structure f excellent in high-speed switching characteristics.11. It is something to do. Recently, due to the progress of miniaturization technology, the high performance of MO8 type semiconductor devices has been significantly reduced, and it is difficult to achieve Kt of high speed operation, which was the domain of bipolar semiconductor devices conventionally replaced by TTL. (-I) Furthermore, cMoS semiconductor devices have the same speed as NMOEI semiconductor devices, but consume only a few minutes of power consumption.
As semiconductor devices become more highly integrated, R111 issues arise.
It is thought that the role of CMo5 semiconductor devices with low power consumption will become increasingly important due to the fact that the devices themselves generate heat.

Therefore, the present invention has been proposed to overcome the conventional problem of sacrificing the switching characteristics of one of the P-channel and N-channel transistors for ease of manufacturing in the 0MO8 element.
Unlike the No. 11 method, it is an optimized version of both PN channel transistors, and the drain capacitance is reduced using bamboo.
, ``Umonodechiru.'' Figure 1 shows an N-type silicon substrate Kpwe.
A conventional example in which ll is formed is shown. In general, the process length of MoS elements is longer than that of NMOEI elements.
・The lightning pressure (v + h, ) is
Select a substrate 101#lN!l- that has a value of 0.5t (0.5t). 1lt1106 thickness 600A will be 5 to 10 x 10"C'. Y, p? nell 2
02 is the stability of V + h, the concentration is 1 to 5
A P-type dopant such as B+ is implanted, and a heat treatment is performed to make the concentration distribution uniform. P channel transistor source drain P+ diffusion layer 104 and N channel transistor source drain N diffusion layer 105, channel striper diffusion layer 107, element isolation oxide film 103, polycrystalline silicon gate FF pole 10 days, aluminum FF1tli wiring 1
09 and passivation fight. Here, MOS
Considering the dispersion capacity of a transistor, in the example of FIG. 1, the drain 1041d of the HP channel transistor,
The junction capacitance between N and the substrate 101 is
Also, the drains of N-channel transistors 105, Pw
A capacitance is formed between the capacitor and the capacitor 102, and serves as the drain capacitance of each PN transistor. This means that the operating area of the MOS transistor is only on the very surface of the substrate. If, 1ii11 is not formed, the transistor is formed in a substrate whose surface density is approximately the same as the concentration, and in a well whose depth is several tens of times greater than the operating area. become,
Since the drain capacity becomes large, the switching characteristics become slow, and for this reason, the 0MO8 element has conventionally been considered unsuitable for high-speed operation. Therefore, P and N of the present invention
The present invention provides an 0MO8 element which reduces channel transistor drain capacitance and is suitable for high speed operation. Before explaining the present invention, let us consider a conventional MOS transistor having a capacity of 2 Yanks and a drain (A) with diffusion layer depths x and i, respectively, with reference to FIG. Is there a substrate with approximately step-like gradient?oe l l (
The depletion layer between B) is the size of the unit area! la becomes. Here, since NrI is the substrate concentration and the others are constants, equation (2) becomes 0%r, and it can be seen that the drain capacitance is proportional to the square root of the substrate concentration. However, in the conventional example, it was impossible to make the ND thinner because of VIA and punch-through prevention IL. Therefore, in order to prevent P+h and punch-through in a region closer to the surface than the drain depth xi, the present invention integrates VIA near the surface on a low-concentration well of a low #marine substrate. A diffusion layer is formed in each case so that the FIG. 2 shows an 0MO8 element structure according to an embodiment of the present invention. As the P-type silicon substrate 201, a material with an impurity concentration R5x101'cm-" or less is used, ideally a silicon substrate with an impurity concentration of R5x101'cm-".
Well 2021d N-type dopants such as phosphorus are ion-implanted and heat-treated to a depth of 3 to 10 μm, with impurity deposits 1 to 1 [
It is formed to have a size of 1 x 10"cm-3.

Element isolation of MOS transistor t■ is done by thermal oxidation 1lQ
The channel strike 9 bar 204, which was carried out with 203f and provided in the N-layer region, is made of a P-type mineral layer. Nwe
Inject 1 to 5 x 10'' side-2 ions of phosphorus into the ll area,
Also, poron was added to the N channel region of the P substrate by 1 to 5
10 "cm-" ion implantation, 1000-1100
Heat treatment of the culm guard for 1 hour at ℃ is carried out to a depth of 05 to 15 μm and the substrate surface concentration Nwell area is 1 to 3 x 10” tyn.
-3, N-type diffusion N4206 and P-type diffusion layer 207 were formed to form N substrate region 1 to 6 x 10" 1. Source and drain diffusion layers of 208 N channel transistors, 2
n5n-p channel source, drain 41A IN I
4, and for the polycrystalline silicon gate electrode 210,
Each was formed by ion implantation using a self-heating table. After the contact hole was opened and the At wiring 209f type TJV was performed, a passivation film 211 was formed. In this embodiment, diffusion ingestion will be explained with reference to FIG. 3. (C) is the concentration distribution in the channel portion of the present invention, and the concentration near the substrate surface is about the same as that of the conventional example (B). Do it. It is assumed that the source/drain diffusion layer (-) has a stepwise distribution (C distribution) with a depth of xj as in the conventional example, and the diffusion layer of the present invention has a depth of xj + ZD and has a substrate concentration or Assuming that the concentration of n, Nwell is Nα, and that the !I curve gradient from xj to Xb+7D is approximately linearly distributed, if we consider yo＜ , (1) (2)
Here, as for X in the depletion layer, the integral equation of formula (3) must be solved, so f (e) = b - αX ......
・(4) If we calculate the drain capacitance from equation (2) using 2, which is simply the same as the conventional example, it will be surrounded by (0) and the X axis between depth xj and X in Figure 3. In this example, it was calculated to be 130% of the drain capacity of the conventional method. (2) Compared to the conventional method, the surface concentration is almost the same, so there is no decrease in l/C, MOF+transistor current increase rate β. Tsukiri, IV+
o s Transistor transfer lIr1 in decrease? r
The structure is suitable for high-speed operation because the drain capacitance is increased and the low-frequency effect is suppressed.

[Brief explanation of the drawing]

Figure 1 is a structural diagram of a conventional 0MO8 element. FIG. 2 is a structural diagram of the Takanaka CMO8 element of the present invention. FIG. 3 shows the impurity concentration distribution in the drain part of the conventional and the present invention. Applicant Suwa nTsha Co., Ltd. Figure 2 χ1 Figure 3

Claims (1)

[Claims] An N-type dopant material is ion-implanted into a part of a P-type silicon substrate with an impurity concentration lower than 5XjO''α1, and a NweIl of 3 to 10 μm is formed by a thermal process; The impurity power of l is below 1X I Q"crn-", P
Forming an N-channel MO8) transistor on a type silicon substrate, and having a substrate surface concentration of 1 to 6×1.
It will be about 016 cm'. Depth [1,5t, p 1
．． Similarly, a P-channel MO transistor is formed in the Nqnel region, and the substrate surface concentration is 1 to 3.
x depth of about 1016cm-3, 05 to 1.
A semiconductor device characterized in that a 5#7T N-type impurity layer is formed.