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JPS609238A - Receiver of spread spectrum signal - Google Patents

Receiver of spread spectrum signal

Info

Publication number
JPS609238A
JPS609238A JP58116417A JP11641783A JPS609238A JP S609238 A JPS609238 A JP S609238A JP 58116417 A JP58116417 A JP 58116417A JP 11641783 A JP11641783 A JP 11641783A JP S609238 A JPS609238 A JP S609238A
Authority
JP
Japan
Prior art keywords
spread spectrum
speed
spectrum signal
transfer
correlation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58116417A
Other languages
Japanese (ja)
Inventor
Kenichi Onishi
謙一 大西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Tateisi Electronics Co
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tateisi Electronics Co, Omron Tateisi Electronics Co filed Critical Tateisi Electronics Co
Priority to JP58116417A priority Critical patent/JPS609238A/en
Publication of JPS609238A publication Critical patent/JPS609238A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J13/00Code division multiplex systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)

Abstract

PURPOSE:To demodulate a spread spectrum signal to a high speed by increasing the number of first-in/first-out FIFO memories, and correlators, etc. by (n) times and therefore obtaining the correlation speed of (n) times as high as the speed of a single correlator. CONSTITUTION:A spread spectrum signal S(t) is converted into a digital value by an A/D converter 1, and FIFO memories 2 and 3 store the output of the converter 1 respectively for each fixed time. The outputs of the memories 2 and 3 are converted into analog values by D/A converters 5 and 6. Then the correlators 7 and 8 secure the correlation between the outputs of converters 5 and 6 and the pseudo random noise/PN code and add it to an adder 9. Thus the transfer speed of the signal S(t) to the FIFO memory is read out and controlled to the double speed by a transfer control circuit. Thus the double correlation speed is obtained by the transfer control circuit compared with a single correlator. As a result, the correlation is possible despite a high speed of the signal S(t). This ensures the demodulation of a high-speed data signal.

Description

【発明の詳細な説明】 〈発明の分野〉 本発明は、スペクトラム拡散通信方式に係り、特にはス
ペクトラム拡散信号受信機に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to spread spectrum communication systems, and more particularly to spread spectrum signal receivers.

〈従来技術とその問題点〉 スペクトラム拡散通信方式1こおけるスペクトラム拡散
信号は、データ信号とPN(擬似ランダム雑音)符号と
の混合信号であり、受信機においてこのスペクトラム拡
散信号からデータ信号を復調するには、スペクトラム拡
散信号とI) N符号との相関をとり、その相関出力の
ピーク値の正負によつてデータ信号を復元している。こ
のスペクトラム拡散信号とPN符号との相関をとる相関
回路には、CCD (Charge Coupled 
Device )を内蔵したトランスバーサルフィルタ
が使用されるが、このトランスバーサルフィルタは転送
りロック速度が遅く、ざらに入力信号の周波数帯域が狭
いために、高速度のスペクトラム拡散信号の復調には使
用できないという難点があった。
<Prior art and its problems> The spread spectrum signal in spread spectrum communication method 1 is a mixed signal of a data signal and a PN (pseudorandom noise) code, and the receiver demodulates the data signal from this spread spectrum signal. In this method, the correlation between the spread spectrum signal and the I)N code is calculated, and the data signal is restored based on the sign of the peak value of the correlation output. The correlation circuit that correlates this spread spectrum signal with the PN code includes a CCD (Charge Coupled
A transversal filter with a built-in device (Device) is used, but this transversal filter has a slow transfer lock speed and a narrow input signal frequency band, so it cannot be used for demodulating high-speed spread spectrum signals. There was a problem.

〈発明の目的〉 本発明の目的は、上述の技術的課題を解決し、スペクト
ラム拡散信号が高速となっても相関を可能とし、確実に
復調できるようにしたスペクトラム拡散信号受信機を提
供することである。
<Object of the Invention> An object of the present invention is to provide a spread spectrum signal receiver that solves the above-mentioned technical problems and enables correlation and reliable demodulation even when the spread spectrum signal becomes high speed. It is.

〈発明の構成と効果〉 本発明では、上述の目的を達成するために、スペクトラ
ム拡散信号をデジタル値に変換するA/D変換器と、A
 / D変換器の出刃を一定時間毎φこ順次記憶するn
 l1ilのF I F O(First In−Fi
rst 0ut)メモリと、前記各FIFOメモリから
の出刃をアナログ値にそれぞれ変換するn個のD/A変
換器と、前記各D / A変換器からの出力とPN符号
との相関をそれぞれとるn個の相関器と、前記各相関器
の出力を加算する加算器と、スペクトラム拡散信号の前
記FIFOメモリへの転送速度を該メモリからの読出し
速度のn倍となるように制御する転送制御回路とによっ
て受信機を構成したので、単一の相関器の相関速度のn
倍の相関速度を得ることができ、これによってスペクト
ラム拡散信号が高速となっても相関が可能となり、確実
に高速のデータ信号を復調することができる。
<Configuration and Effects of the Invention> In order to achieve the above-mentioned object, the present invention includes an A/D converter that converts a spread spectrum signal into a digital value, and an A/D converter that converts a spread spectrum signal into a digital value.
/ Sequentially memorize the cutting edge of the D converter every fixed time φ
First In-Fi
rst 0ut) memory, n D/A converters that convert the output from each of the FIFO memories into analog values, and n that correlates the output from each of the D/A converters with the PN code. an adder that adds the outputs of the respective correlators, and a transfer control circuit that controls the transfer speed of the spread spectrum signal to the FIFO memory to be n times the read speed from the memory. Since we configured the receiver by n of the correlation speed of a single correlator
It is possible to obtain twice the correlation speed, which makes it possible to perform correlation even when the spread spectrum signal becomes high speed, and it is possible to reliably demodulate high speed data signals.

〈実施例の説明〉 以下、図面によって本発明の実施例について詳細【こ説
明する。第1図は本発明の一実施例の要部の回路図であ
り、第2図は第1図に示す回路の各部の信号のタイムチ
ャートである。スペクトラム拡散信号S(りは、第2図
(a)に示されるデータ信号d(す(+1あるいは−1
の2値時系列符号)と、第2図(I))に示されるPN
(擬似ランダム雑音)符号P(す(+1ろるいは−1の
2値打号)との積〔第3図(C)〕になっている。この
スペクトラム拡散信号S(りからデータ信号d(りを復
調するには、受信側においてスペクトラム拡散信号S(
りとPNN符号(【)との相関をとらねばならない。ス
ペクトラム拡散信号S(りから第2図(k) fこ示さ
れる相関信号Sl を得るために、本発明に従うスペク
トラム拡散信号受信機は、スペクトラム拡散信号S(【
)をデジタル値に変換するA/D変換器1と、A/D変
換器1の出力を一定時間毎に順次記憶する2個の第1.
第2−FIFOメモリ2,3と、各FIFOメモリ2,
3の出力をアナログ値にそれぞれ変換する2個の第1.
第20/A変換器5,6と、各D/A変換器5,6から
の出力とPN符号との相関をそれぞれとると2個の第1
.第2相関器7゜8と、前記各相関器7,8の出力を加
算する加算器9と、スペクトラム拡散信号δ〔りの前記
第1゜第2 F I F Oメモリ2,3への転送速度
を該メモリからの読出し速度の2倍となるように制御す
る転送制御回路4とを有して構成きれる。
<Description of Embodiments> Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram of a main part of an embodiment of the present invention, and FIG. 2 is a time chart of signals of each part of the circuit shown in FIG. The spread spectrum signal S(ri) is the data signal d(s(+1 or -1) shown in FIG. 2(a)).
binary time series code) and the PN shown in Figure 2 (I))
(pseudo-random noise) code P (binary code of +1 or -1) [Figure 3 (C)]. To demodulate the spread spectrum signal S(
It is necessary to correlate the values with the PNN code ([). In order to obtain the correlated signal Sl shown in FIG. 2(k) from the spread spectrum signal S (
) into a digital value, and two first .
2nd-FIFO memories 2, 3 and each FIFO memory 2,
two first .
When the correlation between the outputs from the 20th/A converters 5 and 6 and the outputs from the D/A converters 5 and 6 and the PN code is taken, the two first
.. A second correlator 7.8, an adder 9 for adding the outputs of each of the correlators 7 and 8, and a transfer of the spread spectrum signal δ to the first and second FIFO memories 2 and 3. The transfer control circuit 4 controls the speed to be twice the read speed from the memory.

スペクトラム拡散信号S(りは、A/D変換器Iによっ
てデジタル値に変換された後第1.第2FIFOメモJ
2.3iこ一定時間毎に交互に転送される。この第1.
第2FIFOメモリ2,3への転送は、転送制御回路4
からの第2図(d) (e) iこ示す転送りロックS
A、SBによってデータ信号d(【)の1ビツトに相当
するPNN符号(りの1フレーム毎、すなわち一定時間
毎に交互に行なわれる。第1゜第2FIFOメモI) 
2 、3 iこ大刀されたデータは、早い順から転送制
御回路4からの第2図(f)に示す読出しクロックSc
によって読出され、第1.第2D/A変換器5,6にそ
れぞれ与えられ、アナログ値に変換される。この読出し
クロックSc の速度:は、転送りロックSA、SBの
1/2になるように転送制御回路4によって制御される
。第1.第2D / A変換器5,6Iこよって、第2
図(gバh)lこ示すよ知こブナロダ値貞1ζ変換1.
さ、れ1tこ信号SD、5Ell−j:、第1.第2相
関器7.81こよってI) N符号P (t)との相関
がとられ、第2図(す(j)に示すよう昏こデータの1
ビツトおきにデータ信号d(りに応じて正負の相関ピー
クを示す出刃信号SF、SGが得られる。
The spread spectrum signal S (is converted into a digital value by the A/D converter I and then stored in the first and second FIFO memo J
2.3i are transferred alternately at fixed time intervals. This first.
Transfer to the second FIFO memories 2 and 3 is performed by the transfer control circuit 4.
Figures 2 (d) and (e) show the transfer lock S.
The PNN code corresponding to 1 bit of the data signal d([) is generated by A and SB (this is performed alternately every frame, that is, every fixed period of time. 1st and 2nd FIFO Memo I)
2, 3 The data that has been processed is read out from the transfer control circuit 4 by the read clock Sc shown in FIG. 2(f) from the earliest.
The first . The signals are supplied to second D/A converters 5 and 6, respectively, and converted into analog values. The speed of this read clock Sc is controlled by the transfer control circuit 4 so that it becomes 1/2 of the speed of the transfer locks SA, SB. 1st. The second D/A converter 5, 6I, therefore, the second
Figure (gbh)l shows Chikobunaroda value 1ζ conversion 1.
1st signal SD, 5Ell-j:, 1st. The second correlator 7.81 thus performs a correlation with the I) N code P (t), and as shown in FIG.
Detailed signals SF and SG are obtained which exhibit positive and negative correlation peaks depending on the data signal d (bit by bit).

第1.第2相関器7.8からの出刃信号SF、SGを加
算器9によって加算し、これによって元のスペクトラム
拡散信号S(りの1ビツト毎のデータに応じて、第2図
(k月こ示す相関信号Sl が得られることになる。さ
らに受信機でtま、相関信号S■ に基づいて図示しな
いデータ判定回路によってデータ信号d(りの復元が行
なわれる。
1st. The output signals SF and SG from the second correlator 7.8 are added by an adder 9, and the result is that the original spread spectrum signal S is calculated according to the data for each bit of the original spread spectrum signal S. Correlation signal S1 is obtained.Furthermore, in the receiver, data signal d(R) is restored by a data judgment circuit (not shown) based on correlation signal S1.

転送制御回路4は、転送りロック発生回路10と、2進
カウンタ12と、PN符qの1]L/ −ム当りのビッ
ト数に相当する数MのM進カウンタ11と、NOT回路
13と、第1.第2 AND回路14゜15とから成り
、M進カウンタ111こよってPN符号の1フレーム毎
に交互をこ第1.第2FIFOメモリ2,3に転送する
タイミングを作成し、2進カウンタ11によって第1.
第2FIFOメモリ2,3からの読出しタイミングを作
成する。
The transfer control circuit 4 includes a transfer lock generation circuit 10, a binary counter 12, an M-ary counter 11 with a number M corresponding to the number of bits per 1]L/-m of the PN code q, and a NOT circuit 13. , 1st. It consists of a second AND circuit 14 and 15, and an M-ary counter 111 alternately performs the first and second AND circuits for each frame of the PN code. The timing for transferring to the second FIFO memories 2 and 3 is created, and the binary counter 11 is used to determine the timing for transferring the data to the first FIFO memory 2 and 3.
The read timing from the second FIFO memories 2 and 3 is created.

本発明に従うスペクトラム拡散信号の受信機では、第2
図で示されるようにスペクトラム拡散信号の転送の速度
すなわち転送りロックSA、SBの速度は、読出しの速
度すなわち読出しクロックSCの速度の2倍となってお
り、2個の相関器を使用することによって単一の相関器
の相関速度の2倍の相関速度が得られることになる。こ
れによって高速のスペクトラム拡散信号の相関をとるこ
とが可能となり、データ信号を確実に復調することがで
きる。
In the spread spectrum signal receiver according to the present invention, the second
As shown in the figure, the transmission speed of the spread spectrum signal, that is, the speed of the transfer locks SA and SB, is twice the read speed, that is, the speed of the read clock SC, and two correlators are used. This results in a correlation speed twice that of a single correlator. This makes it possible to correlate high-speed spread spectrum signals, and it is possible to reliably demodulate data signals.

前述の実施例では、FIFOメモリ、相関器等はそれぞ
れ2個ずつ設けられたけれども、本発明は2航に限るも
のではなく、複数(n)岡であってもよく、この場合に
は、スペクトラム拡散信号のFIFOメモリへの転送速
度は該メモリからの読出し速度のn倍昏こなるように転
送制御回路昏こよって制御され、単一の相関器の相関速
度のn倍の相関速度を得ることが可能となる。
In the above-mentioned embodiment, two FIFO memories, two correlators, etc. were each provided, but the present invention is not limited to two vessels, but may be a plurality of (n) vessels, and in this case, the spectrum The transfer speed of the spread signal to the FIFO memory is controlled by the transfer control circuit so that it is n times the read speed from the memory, thereby obtaining a correlation speed that is n times the correlation speed of a single correlator. becomes possible.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の要部の回路図、第2図eま
第1図に示された回路の各部の信号のタイムチャートで
ある。 1・・・A / D変換器、2,3・・・第1.t12
FIFOメモリ、4・・・転送制御回路、5.6・・・
第1.第2D/A変換器、7.−8・・・第1.第2相
関器、9・・・加算器。 出 願 人 立石電機株式会社 代理人 弁理士岡田和秀
FIG. 1 is a circuit diagram of a main part of an embodiment of the present invention, and FIG. 2 is a time chart of signals of each part of the circuit shown in FIG. 1. 1... A/D converter, 2, 3... 1st. t12
FIFO memory, 4... Transfer control circuit, 5.6...
1st. 7. second D/A converter; -8...1st. Second correlator, 9...adder. Applicant: Tateishi Electric Co., Ltd. Agent: Kazuhide Okada, patent attorney

Claims (1)

【特許請求の範囲】[Claims] (1) スペクトラム拡散信号をデジタル値に変換する
A / D変換器と、A/D変換器の出力を一定時間毎
に順次記憶するn個のFIFOメモリと、前記各FIF
Oメモリからの出力をアナログ値にそれぞれ変換するn
個°のD/A変換器と、前記各D / A変換器からの
出力とPN符号との相関をそれぞれとるn l1ffi
の相関器と、前記各相関器の出力を加算する加算器と、
スペクトラム拡散信号の前記FIFOメモリへの転送速
度を該メモリからの読出し速度のn倍となるように制御
する転送制御回路とを含むことを特徴とするスペクトラ
ム拡散信号受信機。 (2、特許請求の範囲第1項に記載のスペクトラム拡散
信号受信機1こおいて、 前記転送制御回路は、転送りロック発生器と、転送りロ
ック発生器からのクロックを読出しクロックとするため
のn進カウンタと、PN符号の1フレーム当りのビット
数に対応した数MのM進カウンタとを含み、転送りロッ
ク発生器からの、転送のためのクロックを前記M進カウ
ンタによってPN符号の1フレーム毎に順次前記FIF
Oメモリに与え、前記n進カウンタからの読出しクロッ
クを前記各FIFOメモリおよび前記各相関器に与える
スペクトラム拡散信号受信機。
(1) An A/D converter that converts a spread spectrum signal into a digital value, n FIFO memories that sequentially store the output of the A/D converter at regular intervals, and each of the above-mentioned FIFs.
Convert each output from memory into an analog value n
Correlate each D/A converter and the output from each D/A converter with the PN code.
a correlator, and an adder that adds the outputs of the respective correlators;
A spread spectrum signal receiver comprising: a transfer control circuit that controls the transfer rate of the spread spectrum signal to the FIFO memory to be n times the read rate from the memory. (2. In the spread spectrum signal receiver 1 according to claim 1, the transfer control circuit includes a transfer lock generator and uses a clock from the transfer lock generator as a read clock. and an M-ary counter with a number M corresponding to the number of bits per frame of the PN code, and the clock for transfer from the transfer lock generator is applied to the PN code by the M-ary counter. The FIF sequentially for each frame
A spread spectrum signal receiver for providing a read clock from the n-ary counter to each of the FIFO memories and each of the correlators.
JP58116417A 1983-06-27 1983-06-27 Receiver of spread spectrum signal Pending JPS609238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58116417A JPS609238A (en) 1983-06-27 1983-06-27 Receiver of spread spectrum signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58116417A JPS609238A (en) 1983-06-27 1983-06-27 Receiver of spread spectrum signal

Publications (1)

Publication Number Publication Date
JPS609238A true JPS609238A (en) 1985-01-18

Family

ID=14686555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58116417A Pending JPS609238A (en) 1983-06-27 1983-06-27 Receiver of spread spectrum signal

Country Status (1)

Country Link
JP (1) JPS609238A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5789616A (en) * 1996-01-26 1998-08-04 Bridgestone Sports Co., Ltd Method for production of zinc acrylate
US6270209B1 (en) * 1999-03-19 2001-08-07 Canon Kabushiki Kaisha Ink tank
US6958532B1 (en) 1999-06-18 2005-10-25 Nec Electronics Corporation Semiconductor storage device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5789616A (en) * 1996-01-26 1998-08-04 Bridgestone Sports Co., Ltd Method for production of zinc acrylate
US6270209B1 (en) * 1999-03-19 2001-08-07 Canon Kabushiki Kaisha Ink tank
US6958532B1 (en) 1999-06-18 2005-10-25 Nec Electronics Corporation Semiconductor storage device

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