JPS6079564A - Address control circuit of dad player - Google Patents

Abstract

PURPOSE:To control the address of a memory where symbols read out from a disc are stored by providing the second adding means which adds the reference address outputted from a reference address output means and the relative address outputted from the first adding means. CONSTITUTION:A player reproduces symbols W0-W23, which are written on the disc in accordance with a format shown in a figure, as a music signal. A signal INP is read out from the disc through an optical system is inputted to a receiving circuit 2. A reference address generating circuit 1a outputs a reference address EADR, which is used when symbols U0-U3 outputted from a buffer register 4 are written, and a reference address MADR which is used when symbols U0-U3 in an RAM6 are processed and a signal CAC is outputted. A relative address generating circuit 1b outputs a relative address RADR, and an adder 1c adds the reference address EADR or MADR and the relative address RADR. The output of the adder 1c is supplied as an address signal ADS to an address terminal AD of the RAM6.

Description

[Detailed description of the invention]

This invention is DAD (Digital Audio Disk)
The present invention relates to an address control circuit used in a player. (Background Art) As a method for correcting 834 data errors in digital audio, CIRC (Cross Interleaving), which is a combination of Reed-Solomon code and cross interleaving, has been used in recent CD (combination disc) discs.
An error B1 correct method with ve Reed -8olomon Code) is used. In the CD player X7 to which this CI RC error correction method is applied, the music signal data read from the disc is temporarily stored in the memory, and the unstored data is read out to check for errors, correct them, and correct them. The data is output to a DAC (digital/analog converter), etc.
At this time, it is necessary to control the address of the memory in a complicated manner. The present invention also relates to an address control circuit that performs at-1-no-1-lil control of the memory. First, an outline of a CD system to which an error detection method using CI RC is applied will be described. This error detection method is a known method, and is detailed in, for example, Japanese Patent Laid-Open No. 57-4629. FIGS. 1 and 2 are a conceptual diagram of a write circuit that writes data to a disk, and a schematic diagram of a processing circuit that processes data read from the disk, respectively. In FIG. 1, the symbols 16n, R6n, ..., R
6n-1-5 are each 16-bit musical tone data,
Each musical tone data is an 8-bit symbol Wl 2n,A. Wl 2n , B-=-=VJ12n -1-11,
Processed in units of B. Total of 24 symbols Wl 2+1
, A... (Well, first, it is selectively delayed by two delay times in the delay section D Iyl, then the order is changed by (1) in the cross section C1os1, and then the Reed-Solomon code is input by the parity circuit Pa1. Error detection symbols Q12n to Q12n +
3 (8 bits each) are added. Then, the symbols Q121) to Q12'n +3 are added, resulting in a total of 28 symbols, which are sent to the delay unit Dly2 C3 and delayed again (interleaving). Note that this delay section D
In ly2, D=4 delay time. Next, in the parity circuit Pa2, the symbol 1) 1.2n is again used for data error detection based on the Reed-Solomon method.
-Pl 2n +3 (each 8 hits 1-) are converted into a total of 32 symbols, and these 32 symbols are selectively delayed by one delay time in the delay section Dly3, and then the data error detection symbol P , Q are inverted by an inverter to form a data group DWD for disk writing. This i′-ta group DWD is sequentially EFM (Eigt to Fou
rteen ModulaLi'on) and written to disk. Figure 3 shows each symbol recorded on the disk! , : is a diagram showing the state. In this diagram, 5YNC is a synchronization pattern added when writing to a disc, WO to W23 are symbols corresponding to music signal data, QO-C3, PO-R
3 are symbols for error correction. Then, up to 5YNC-R3 shown in the figure becomes a processing unit for error correction and is called a frame Fr. Furthermore, if the symbol is delayed by one day delay time, it will be written in the frame Fr next to the frame Fr to which it would be written if the symbol was not delayed. Next, during data reproduction, the data read from the disk is demodulated by the EFM demodulation circuit and returned to the data group DWD at the time of disk writing. This data group DW
Each symbol of D is first processed by a delay unit D 11 shown in FIG.
//I to J: is selectively delayed by 1 day delay time,
As a result, the symbol time shift based on the delay unit Dly3 in FIG. 1 is corrected. And an error detection symbol P. Q is supplied via an inverter, and other symbols are supplied directly to the C1 decoding circuit CI dec. The C1 decoding circuit C1dec calculates a syndrome based on each symbol, detects an error symbol from the sieved syndrome based on the Reed-Solomon coding method (error detection based on the symbol P), corrects the symbol, and outputs it. . C1
Each symbol output from the decoding circuit C4dec is
It is delayed by the delay unit DIV5, thereby correcting the approximately -h deviation of the symbols based on the delay unit DIv2 shown in FIG. 1, and is supplied to the C2 decoding circuit C2dec. The C2 decoding circuit C2dec detects and corrects error symbols in exactly the same manner as the C1 decoding circuit C1dec (error detection based on symbol Q), and outputs corrected symbols. Each of the output symbols is sent to the cross section ClO32 and their order is changed by C3, thereby reversing the permutation performed by the cross section Cl03I of FIG. Next, it is selectively delayed by two symbol times in the delay unit D1y6, thereby delaying the delay unit DI in FIG.
The symbol time shift due to VI is corrected and returned to Rakuhata data L'6n...R6n+5. Soshi-
(, these musical tone data L611...R6n+
5 is sequentially supplied to the DAC and converted into an analog signal,
A musical tone is produced from the speaker. The above is an outline of the CD system to which the CIRC error detection method is applied. In addition, in the conceptual diagram mentioned above,
Although the memory for symbol storage is not shown, each symbol read from the disk is actually stored in the -H memory, and each process (including delay processing) in FIG. This is done by reading out. [Object of the Invention] The present invention provides an address control method that can perform address control of a memory in which symbols read from a disk are stored with a minimum hardware configuration in a DAD player using a CIRC error detection method. The purpose is to provide circuits. [Characteristics of the Invention] This invention is characterized by having the following constituent elements. (a) Reference address output horn means for outputting a W quasi-address. (b) A memory in which a plurality of address data are stored in advance. (C) A plurality of counters that are pulled in accordance with the mode of address control and control reading of address data in the memory. (d) Outputs of the plurality of counters are selectively controlled in the memory. A first selection means that supplies the data to the address terminal. (e) A second selection means that selectively outputs a plurality of address data read from the memory. <r> Each output of the second selection means (1) A reference address output from the reference address output means and a relative address output from the first addition means. Second addition means for adding D?, (Explanation of Embodiment) FIG. 4 shows an address control circuit 1 according to an embodiment of the present invention.
FIG. 1 is a block diagram showing the configuration of main parts of a 7j CD player to which the 7j CD player is applied. The CD player shown in this figure has symbols W written on the disc according to the format A-mat shown in FIG.
It reproduces O to W23 as musical tones, and embodies each process shown in FIG. 2. First, a general description of FIG. 4 will be given. [Outline of FIG. 4] In FIG. 4, the signal INP is a signal (EFM modulated signal) read out from the disk via the optical system,
This signal IN1] is input to the receiving circuit 2. The receiving circuit 2 receives the synchronization pattern 5YNC included in the signal 1'NP.
Based on the EFM frame synchronization signals VFSY and NG are created and output to the address control circuit 1, and the signal INP
Each data pin except for the synchronization pattern 5YNC is outputted to the EFM demodulation circuit 3, and the signals INP to EF
M clock palace φ. is reproduced and output to the EFM demodulation circuit 3 and buffer register 4, and each symbol WO
-, W23, Q, O~Q3. A symbol synchronization signal DSY is output to the buffer register 4 at the beginning of PO-R3. In addition, in reality, E, F M data pulse φ
Cross pulses φoa, φ with 180° phase difference as 0
Each ob is created, but here they are collectively called φ
. It is shown in The EFM demodulation circuit 3 demodulates the EFM modulation 8' Iζ 1 symbol - 14 bits of channel pit 1 to the original symbol of 1 symbol = 8 bits, and sequentially outputs it to the buffer register 4 in series. The buffer register 4 is a register that temporarily stores symbols supplied from the EFM demodulation circuit 3, and includes a serial-to-parallel conversion circuit that converts serial data output from the EFM demodulation circuit 3 into parallel data and a plurality of registers. The output is supplied to the gate circuit 7. The write control circuit 5 is a circuit that controls writing and reading of the buffer register 4, and when the control signal EFMD is supplied from the address control circuit 8, the write control circuit 5 outputs the control signal WE.
are output to the read/write 1 to control I terminal R/W of the RAM (random access memory) 6 and the control terminal of the gate circuit 7, respectively. As a result, RAM6 becomes writable f
At the same time, the gate circuit 7 becomes open, and the data in the buffer register 4 becomes
RA via AM6 write data bus DABS1
The signal is supplied to M6 and written into the address output from the address control circuit 1. Further, this write control circuit 5 sends a control signal VSYMB to the address control circuit 1 at the time when the data in the baffle register 4 is output to the RAM 6.
Output to. RAM6 stores each symbol WO~W read from the disk.
23. QO~Q3. There are two bytes of memory in which PO-P3 and the flags to be described are stored. As shown in Figure 4
As mentioned above, the CD player A7 performs each process shown in FIG.
Delay processing by ly4, Dly5, and Dly6 is performed using this RAM6. That is, the RAM 6 stores symbols in a number corresponding to the amount of delay of each symbol. For example, the symbol WO
requires a delay of 27D (108), so RAM6 retroactively stores 109 (10,8+
More than 1 (actually 119) symbols are stored. When decoding C2, the symbol WO stored 108 frames earlier is used. The same applies to other symbols. Address control circuit 1 uses symbols WO-W23゜QO~Q
3. Write address when inputting and outputting PO to P3 to RAM 6, read address from RAM 6 of symbols required when performing C1 decoding and C2 decoding, RAM 6
Symbols WO to W23 (however, in this case, WO to W
23 is Dly4 to Dly6. Create a read address etc. when outputting the symbol after considering C, los 2) to a DAC (digital/analog converter: not shown), and write it to the RAM as an address signal ADS.
This is a circuit that outputs to the address terminal AD of No.6, and the eT line will be described later. Data error detection/correction circuit 8 includes C1 decoding and C2 decoding.
This is a circuit that performs decoding. That is, first, during C1 decoding, symbols WO to W23 are sequentially read out from RAM C3 under the control of the address control circuit 1.
．． QO-Q3. PO~P3 (However, in this case, D ly
4), which is the symbol after considering 4, and read lυ
Then, syndromes 5o-83 are calculated based on each symbol, and based on the calculated syndromes SO to S3, the presence or absence of data errors, the presence or absence of single errors, the presence or absence of double errors, or the presence or absence of triple errors or more are determined respectively. To detect. and,
If there is no data error, set flag EO II I I
I is output to the error flag determination circuit 10, and if there is a single error, "1" is output as flag I31, and if there is a double error, "1" is output as flag E2, and triple error is output. If there is an error or more, flag NE2 is set to “1”.
Output. Further, if there is a single error, for example, only symbol Wj is incorrect, data j indicating the position of the symbol Wj is output to the address control circuit 1, and if there is a double error, for example, symbol Wk is , Wl are incorrect, data indicating the positions of the erroneous symbols Wk and Wl are output to the address control circuit 1, respectively. In this case, the address control circuit 1 assigns data j,
Error symbols Wj, Wk, Wl based on each of I
Create an address and output it to RAM6. As a result, the symbols Wj, Wk, and Wl are read out from the RAM 6, respectively. The data error detection/correction circuit 8 uses the symbol Wj
, Wk, and Wl, and correct them to obtain the correct symbol wJ. It is output to the data bus DA13S,1 as Wk and Wl. At this time, the address control circuit 1 again outputs the addresses of the symbols Wj, Wk, and Wl to the RAM 6. As a result, error symbols in the RAM 6 are corrected. Exactly the same operation as above is performed during C2 decoding as well. However, the symbols read into the data error detection/correction circuit 8 during C1 decoding are WO to W23. QO～Q
3. There are 32 symbols from PO to P3, but the symbols read during C2 decoding are WO to W23. The total of QO to Q3 is G128 (see Fig. 2). Further, in this data error detection/correction circuit 1, musical tone data WO-W
23, and error correction data QO to Q3. l〕To O・1〕
3 cannot be distinguished. That is, these errors a] normal data QO to Q3. It is also possible to detect errors in PO to P3. The error flag determination circuit 10 first detects the flag [0
~E2. A 01 flag is created based on NF2 and output to the data bus DABS2. At this time, the address control circuit 1 outputs an address signal ADS indicating the 01 flag write position to the RAM 6. Here, the 01 flag is the C1 decoded symbol WO~
W23. 'QO~Q3. This flag becomes 1'' when there is a high possibility that an error symbol is included in PO to P3, and becomes 0'' when the possibility is small. Next, in this error flag determination circuit 10, the data error detection/correction circuit 8
During decoding, the 01 flag read from the RAM 6 is input under the control of the address control circuit 1, and this 01 flag and the flag EO~ output from the data error detection/correction circuit 8 during C2 decoding are input. E2. Create C2 Norag based on NE2 and connect data bus DABS2
Output to. At this time, the address control circuit 1 outputs an address signal ADS indicating the writing position of the 02 flag to the RAM 6. Here, the C2 flag is a flag indicating whether or not each symbol WO-W23 is uncorrected (more precisely, whether there is a considerably high probability that it is not corrected), and is a flag indicating whether or not each symbol WO-W23 is uncorrected. 1"° is written in RAM 6. The flag detection circuit 11 is a circuit that checks the above-mentioned C2-flag. When the above-mentioned C1 and C2 decoding is completed, the symbol in RAM 6 WO～W
23 are sequentially read together with the 02 flag under the control of the address control circuit 1 and output to the data bus DABS2,
It is supplied to the parallel/serial conversion circuit 12. At this time, the flag detection circuit 11 checks the 02 flags added to each of the symbols WO to W23, and
It is determined whether or not W23 is uncorrected, and if it is uncorrected, a control signal TE+ is output to the correction circuit '13. The correction circuit 13 detects whether the data output from the parallel/serial conversion circuit 12 is uncorrected data based on the control signal TEI, and outputs it as is if it is uncorrected. If so, the data is corrected using linear interpolation or front-end retention, and is output to the serial/parallel conversion circuit 14. The serial/parallel conversion circuit 14 converts the serial data output from the correction circuit 13 into parallel data and outputs it to a DAC (path shown). The output of this DAC is supplied to a speaker or the like to generate musical tones. Further, the timing control circuit 15 is connected to the crystal oscillator 1.
It generates a clock pulse φ based on the clock pulse φ, and also generates various control signals that use the clock pulse φ as a time base, and outputs them together with the clock pulse φ to each part of the device. The above is the (]'A omitted) of the CD player A shown in FIG. 4. Next, details of the buffer register 4 and write control circuit 5 will be explained. [Details of the buffer register 4 and write control circuit 5] ] 5th
FIG. 2 is a block diagram showing the configuration of buffer register 4 and write control circuit 5. Referring to FIG. In this figure, 4a is an 8-bit shift register that sequentially shifts and stores two signals supplied from the EFM demodulation circuit 3, and performs a shifting operation in synchronization with the FFM clock pulse φ0. A latch section 4b latches each bit output of the shift register 4a at a timing to be described later, and performs serial-parallel conversion of data. 4c, 4d, 4
e is a first, second, and third stage buffer to which the output of the latch section 4b is transferred as appropriate, and each buffer is composed of a register R, etc., ΔAgate OR, and two ant games, j-ANa, and ANb. 8 units are installed in parallel.

[It is configured so that it can be played.] J5, each O mark on the input horn line (straight line) of the AND gate represents an input <, and in the following explanation, the first and second ...This will be called the input end. The above-mentioned first, second and third stage buffers 4c, 4d, z
Each of the registers R, R, . Next, 5
a is a timing generator, and the EFM clock pulse φ
. It consists of a first timing generation section 58-1 that operates in synchronization with the internal clock pulse φ, and a second timing light generation section 5a-2 that operates in synchronization with the internal clock pulse φ. The first timing generating section 5a-1 delays the symbol synchronization signal 1)SY supplied from the receiving circuit 2 by 8 bits to create a latch signal r11, and also generates a timing signal]
-' (see FIG. 6(c)) is set to the second timing generator 5a.
-2. When the second timing generating section 5a-2 is supplied with the timing signal T', it outputs the timing signal T after a predetermined period of time has elapsed. Also, AN
1 to AN9 are AND gates, OR1 to OR4 are A agates, and LO and R1 to R3 are registers. In this case, all of the registers LO, R+ to R3 output their contents at the rising edge of the internal clock pulse φ. Next, 7 is a gate circuit, as shown in the figure.
It consists of eight MO8 type 1" Fl- (MOS type field effect) transistor gates. Next, the operation of the balance register 4 and the write control circuit 5 will be explained with reference to FIGS. 5 and 6. First, it is assumed that all registers are cleared in the initial state.Then, when the serial data demodulated from the EFM demodulation circuit 3 is sequentially supplied to shift 1 to register 4a, the shift to 8 bits 1 is performed. data is supplied to the shift register 4a, and at this point, a latch signal ru (not shown in FIG. 6(b)) is output from the first timing generator 5a-1. Each bit output of the register 4a is latched.Next, the first timing generator 5a
-1 outputs the timing signal T' after a period 1-o has elapsed after outputting the latch signal ru. This period 1-o is set in anticipation of the 1.1° period until the data ((bo) in the same figure) reliably rises on the output side during the latch operation of the latch section 4b. The period between the second and third pulses II of the clock pulse φ0 is set. Further, the timing signal T' is set so that G is "1" for a predetermined period, and this period will be described later. Then, when the timing signal @T' is output, the second timing generating section 5a-2 outputs the timing signal T at the next rising edge t1 of the internal clock pulse φ. When the timing signal T is output, all the input terminals of the AND gate AN2 become "1", and as a result, the AND gate A
Signal LOAD 2 is output from the output end of N2 (FIG. 6 (g)). When the signal LOA[) is output, the output of the AND gate AN4 becomes 1'', and at the next rising edge of φ, "1" is set in the register R1, and each AND gate of the first stage buffer 4G The second input terminal of ANb is all 1″
Each bit output of the latch section 4b is supplied to the registers R, R, . . . via the AND gates ANb, . However, at this point, the data in the latch section 4b is transferred to the first stage buffer/4c. On the other hand, when register R1 is set to 1'', inverter INV1
The output becomes "0" and the signal LOAD is stopped. Furthermore, during the period when the timing signal T is output, the output of the register Lo is fed back to the second input terminal of the AND gate AN1, so the contents of the register Lo are always “
1''. Then, when 1'° is set in the register LO, a signal is generated by the inverter INV2 and inhibits OA D, so the timing signal [is output from J
The signal 1-OAD is never output more than once between IIJ. That is, the data in the latch section 4b will not be transferred to the first stage buffer 4c redundantly. Next, for understanding, let's focus on the data transferred into the first stage buffer 4c and the register RI. Now, in the above-mentioned operation, the data transferred from the latch section 4b is stored in each register R, R... in the first stage buffer 4c, and the data transferred from the latch section 4b is stored in register J3. 1
" is set. At this time, since the output signal @B2 of the register R2 is "0", the AND gate ANb in the first stage buffer 4d is set. The second terminal of ANb... becomes 1'', and as a result, the output signal of each register R, R... in the first stage buffer 4C becomes each AND in the second stage buffer 4d. It is supplied to each register R, R, etc. in the second stage buffer via gates ANb, ANb, etc., and at the next rising edge of φ, 82 becomes "1" and data is obtained in each register. . Furthermore, when the signal B2 is "O'', the outputs of the at gates ANa, . . . in the first stage buffer 1 are "O'', so all registers in the first J32 buffer R, R... are cleared. That is,
The data in the first stage buffer 40 is transferred to the second stage buffer 4d, and the first stage buffer 4C becomes empty. In this case, in exactly the same way, the output signal B1 (“1”) of the register R1 is supplied to the register R2 via ANDGOO1 to AN6, and 1” is set in the register R2, and the register R1 is set to “0”. Then, at the timing of the next internal clock pulse φ, the data in the second stage buffer 4c is transferred into the third stage buffer 4e, and the data in the second stage buffer 4d is transferred in exactly the same way as in the above case. becomes empty and also register R3
is 1", and register l (2 becomes "0". Then, at a predetermined timing, when the control signal EFMD is supplied to the second input terminal of the AND gate AN9, the AND gate A
The control signal WE, which is the output signal of N9, becomes "1", and as a result, groups 1 to 7 are opened, and the data in the third stage buffer 4e is transferred via groups 1 to 7 to the data bus 0ABSl (
(Fig. 4). Since this l1rJ, the output signal of the AND gate AN7 becomes it O11, the register R3 becomes 0'' at the next timing of φ. As mentioned above, the data latched in the latch section 4b is sequentially transferred to the subsequent buffer. Also, the contents of registers R1 to R3 are "1" when there is data in the corresponding buffer, and "o" when it is empty. Here, the data is stored in buffer 1 in the subsequent stage. Explain the data transfer operation of the front-stage Barafun when
11- Do. For example, when data is transferred from the first stage buffer 4C while data is stored in the second stage buffer 4d. In this case, since the output of register R2 is 1'', the output signal of inverter IN3 is ``0''.
becomes PA, and AND GO 1 to AN in the second stage buffer 4d
7j, when each second input terminal of b, ANb... becomes 0'', data is transferred from each register R11 (...) in the first stage buffer 4C to registers R, R... of the second stage buffer 4d. is not performed.Furthermore, at the first input terminals of the first stage buffer 4C,
Since the signal 82 at the "'1" level is supplied, and the output signals of the registers R, R, etc. are fed back to its second input terminal, in this case, the first
Each register R1R . . . in the stage buffer 4C holds its respective storage contents. Like this, the second stage buff? If is not empty, no data is transferred and the data is held. FIGS. 6(S) to 6(W) show the waveforms of each part when the timing signal T is output when the first stage buffer 4C and the second stage buffer 4d are not empty. At time t1, both signals B2 and B+ are "1".
(Figure 〈S〉, (NU)). And time 1
2 (at the rising time of internal clock pulse φ), the data in the second stage buffer 4d is transferred to the third stage buffer 4e, and the signal @B2 becomes "0".
, at the next rise time t3 of the internal clock pulse φ, the data in the @1 stage buffer 7' 4 Q is transferred to the second stage buffer 4d, and the signal B1 becomes '0'.Then, the signal B1 becomes '0'. o”, the inverter INV
The output signal of I becomes 1'', and as a result, the AND gate A
Load low @knee OAD is output from N2 (see Figure 4), and the latch section 4. The data in b is stored in the first stage buffer 4.
Transferred to c. In this case, the output of the register [0 becomes "1" at the 118th time t4 of the next rising edge of φ, as shown in FIG. In this way, when the first stage buffer 4C is empty (Fig. 6 (
) to (ch)), the first stage J3 and the second stage buffer 4c
, 4d are not empty ((S) to (W) in the same figure), the timing at which the signals 10A and D are output is different ((I) to (L) in the same figure). By the way, when the timing signal T' falls by 1"L, the timing signal -1 rises at the next rising edge of the internal clock pulse φ, as shown in FIG. ' (that is, the period when the timing signal T' is '1') is the period until the next latch signal ru is output (or until the symbol synchronization signal DSY is supplied). period), and is set to a length sufficient to transfer data to the first stage buffer 4C. Further, as described above, the output signal of the AND gate ΔN9 is transmitted to the gate circuit 7 via the control signal WE.
and RAM 6 /\, and is also supplied to the address control circuit 1 as a control signal VSYMB. The details of the buffer register 4 and write control circuit 5 have been described above. Next, the Atonenos control circuit 1, which is an embodiment of the present invention, will be described in detail. [Details of address control circuit 1] The basic concept of address control of RAM 6 will now be explained using a simple model. Now, the number of symbols in one frame Fr is 4 symbols UO to U3 as shown in FIG. shall be recorded. It is assumed that there is no delay processing in the delay units [) lyl and D ly3 and replacement processing in the cross unit Cl081 in FIG. 1. In this case, the original symbol before Chikanobu processing (that is, the symbol corresponding to the leftmost symbol in FIG. 1) is recorded on the disk in a distributed manner at the J position indicated by O in FIG. Become. Therefore, C
2 de]-code or to output each symbol to the DAC,
For each /2: -(-6, 4, 2, 0 frames ago, the symbol recorded in the previous frame Fr is required. In other words, the symbol (for each of JO to U3, 7
, 5, 3.1 storage areas (1 area = 8 pits 1~) are provided in RAMe, and the past 6.4.2. It is necessary to go back to O frames and store symbols UO to U3 in memory. Furthermore, in this embodiment, in J5, writing of symbols read from the disk, processing of symbols in R'AM6 (CI, C2 decoding, etc.), and output to DAC are performed in parallel in a time-sharing manner. Therefore, RAM 6 has one area for reloading corresponding to each of the symbols UO to U3, one area for symbol processing, and one area for DAC output. It is necessary to set up one area. As a result of the above, in this model, J3 has the symbol UO~
9, 7.5.3 areas are required corresponding to each of U3. Therefore, the capacity of the RAM 6 is set to 24 areas. Next, FIG. 8 is a block diagram showing the basic configuration of the address control circuit 1. In this figure, a reference address generation circuit 1a generates a standard address E A used when writing symbols UO to U3 output from a buffer register 4.
l) R and the reference address MA used when processing symbols UO to U3 in RAM 6 and outputting the DAC.
The relative address generation circuit 1b is a circuit that outputs the relative address RADR, and the adder 1C is a circuit that outputs the reference address EADR or M.
This is a circuit that adds ADR and relative address RADR. Then, the output of adder 1C is the address signal A I)
The signal S is supplied to the address terminal AD of the RAM 6. Next, the basic concept of address control will be explained. (D Write control of symbols UO to U3 FIG. 9(A) is a schematic diagram of the storage areas of the RAM 6. In this figure, O to 23 indicate the absolute addresses of each area, and <Q> to <8>
indicates a relative address J-0 First, symbols UO to U3 are written in the following manner. First, the reference address FA
DR is set at an arbitrary position, for example, at absolute address 6 as shown in FIG. 9(a). Then, 9 areas from this reference address EADR, that is, absolute addresses 6 to 14
relative area 5EO, the first seven areas, that is, absolute addresses 15 to 21, are relative area SE1, and the next five areas, that is, absolute addresses 22, 23° 0', 1.2, are relative area SE2.
, the next three areas, that is, absolute addresses 3 to 5, are defined as relative areas SE3. Then, the symbol C output from the buffer register 4
10-U3 are sequentially placed in each of the leading addresses of relative areas SEO to SE3, that is, relative address <0> (see O mark). Next, when the E1M frame synchronization signal VFSYNC is supplied, the reference address EA is
Change the DR to an address one address lower. As a result, the relative areas SEO to SE3 are also shifted by one address. In this state
5, sequentially block each phase of symbols UO to U3 output from buffer 7 register 4 1 @ S E O to SE3
Write into relative address <0>. Below, Figure 9 (c), (
The above process is repeated as shown in d). By repeating this process, ', there are 8 symbols UO in the relative area SEO, and 1 symbol () in the relative area S E 'l.
, 4 symbols U2 in the relative area SE2, and 2 symbols U3 in the relative area SE3 are always stored. Further, new symbols u o -U'3 are sequentially written to the relative address <0> of each relative area SE O-8F3. a3, if the reference address EADR matches the absolute address O, the next EFM frame synchronization signal V
, FSYNC is supplied, the reference address FADR
becomes absolute address 23. Therefore, the address control in the above write operation is
The relative addresses RADR used when writing the symbol uo-U3 are rOJ, r9J, respectively. r9+7-'16J, r9+7-t5=21J, therefore, these values rOJ~'17' may be distributed in advance into the relative address generation circuit 11). In addition, the reference address EADR and relative address RAD
If the sum of R is r2/IJ, r25J..., then of course r1. riJ... must be corrected, but in binary operations, this correction can usually be easily made by cutting carries. (i) J Ship 8 and output control during CI and C2 decoding FIG. 10 is a diagram in which the relative areas 5EO-8E3 in FIG. 9 are arranged vertically. The following will explain using this figure. In this figure, symbols U O to () 3 including 11 are placed in the area of relative address <Q> of each relative area SE O-8F 3 by row Ic1, and '1 frame F' as described above.
After writing of r is completed, all symbols in each of the relative areas SEO to SE3 are shifted downward by 1 rear before writing of the next frame Fr is started. J3, this situation will be clear by referring to FIG. And C1
Processing such as decoding, C2 decoding, etc. is blocked by each phase 14SEO
-3E3, based on the symbol in the area at relative address <1> or higher (the area within the broken line in FIG. 10). That is, in C1 decoding (see Figure 2), the symbols within each relative address of relative area SEO-8E3 are sequentially read and processed, and in C2 decoding, the symbols in each relative address of relative area SEO Address <7>, SEL No. 5
>, 5I=2<3>, and each symbol in <1> of SF3 is read out and processed. Address control in the above case is performed as follows. First, the reference atray MADR is set at the 1'' position shown in FIG. Then, during C1 decoding, the relative addresses RADR are respectively rOJ, r9J, r9+ corresponding to each reading of the symbol LJO-U3.
7=16J, r9+7+5=21J, and C2
At the time of decoding, the relative address RADR is set to "O'+6j" corresponding to each reading of symbols UO to U3.
, r94-41, r 16 +2 J , r 21-1
-0''. 0 Read control at the time of DAC output The symbols within the broken line in FIG. 10 are symbols that are being processed and cannot be output to the DAC. Therefore, each relative area SEO~SE3 noku8>, <6>, <4
>, <2> symbols within addresses are output to the DAC. Address control in this case uses MADR as the reference address, and sets relative addresses RADR as r7j, r14J, r19J, and r2 in response to each reading of symbols Uo to U3.
2J What should I do? The above is the idea of address control3. By the way, the above idea is based on the jitter (
This can be achieved only when there is no fluctuation in the read signal (based on fluctuations in the rotational speed of the disk), and in reality there is jitter, so it is difficult to control the address based only on the above concept. This situation will be explained below. First, symbol processing (C1, C2 decoding, etc.) and DAC output for one frame Fr in the RAM 6 are all performed in a frame processing cycle (with the internal clock pulse φ created using a crystal oscillator as a time base).
within a certain period of time). Also, at the end of this frame processing cycle, the internal frame synchronization signal X I=S
YNC is revealed. The internal frame synchronization signal X F S 'YNC and the above-mentioned FFM frame synchronization signal VFSYNC are theoretically synchronized. That is, the rotation of the disk is controlled in synchronization with the internal frame synchronization signal XFSYNC. However, in reality, rotational unevenness occurs due to a delay in response of the disk rotation control system, etc., and therefore jitter occurs in the read signal. Now, due to jitter, the EFM frame synchronization signal VFS
Suppose that the cycle of YNC becomes shorter than the cycle J: of the internal frame synchronization signal XFSYNC. In this case, 1 frame F
The symbol will be written again before the symbol processing and DAC output for r are completed. To explain FIG. 10, the ml address EADR changes to an address one address younger than the symbol processing and DAC output for one frame, and therefore each of the relative areas 5EO-8E, 3 Each symbol is shifted down one area. As a result, each symbol within one rear at the bottom of each of the relative areas SEO to SE3 is erased, making it impossible to perform AC output at all times. On the contrary, EFM7 Ray 1nllllJ ShinfiVFsYNc
The cycle of is the internal frame synchronization signal
If it becomes longer than the synchronization of 1 frame Fr read from the disk, that frame (frame being written in Ju) before all symbols have been written for one frame Fr read from the disk.
This means that symbol processing will start for . In Figure 10, the reference address MADR during symbol processing is the reference address MADR during symbol writing (
This results in a match with YoheDR and -c, making correct symbol processing impossible. Therefore, in this embodiment, as shown in FIG.
A plurality of areas (indicated by diagonal lines fq) for absorbing jitter are provided above and below each of the relative regions SEO to SE3. SoshiC
, the reference address EADR at the time of symbol writing is always set to address <0> of the relative area SEO, as in the case of FIG. 10, thereby making the symbol read from the disk <
The reference address MADR during symbol processing is set to the <3> address (EArlR+3>) of the relative area SEO when there is no jitter. Note that the reason why the 3> address is set is In the example of Fig. 11, in the embodiment described below, -C has four areas each on the upper and lower sides as jitter absorption areas, and the reference address MADR when there is no jitter is set to EADR+4. By doing this, even if the period of the EFM frame synchronization signal VFSYNC is shortened and each symbol is shifted downward in FIG.
The symbols that should be output to are not deleted, and
Even if the period of the EFM frame synchronization signal VFSYNC becomes longer and the reference address MADR moves to one side in the figure, the reference address ~IADR will change to the reference address EAD.
It does not overlap with R. The above is the basic concept of address control. Next, details of the address control circuit 1 will be explained with reference to FIGS. 12 to 19. FIG. 12 is a block diagram showing the details of this address control circuit 1, and the configuration of each part will be explained below. [Configuration of address control circuit 1] In the figure, DAC symbol counter 31, c1/C2
Both the symbol counter 32 and the FFM symbol counter 33 are 5-bit binary counters, and are reset when a "1" signal is supplied to their reset terminal R.
Further, when the 1111+ signal is supplied to the increment terminal ING, the output data is incremented at the timing of the clock pulse φ. The ROM 34 is a ROM for converting the output Do of the DAC symbol counter supplied to its address terminal into another value, and its contents are as shown in FIG. I? The rectifier 35 is a circuit that selectively outputs the data supplied to its input terminals 11 to I4, and when the "'1" signal is supplied to its rect terminal Se1, it outputs the data of the input terminal 11. ,...
..., when the "1" signal is supplied to the input terminal Se4, the data of the input terminal I4 is outputted.
OM, and the contents of each memory area 1@36a to 36e are the 14th
As shown in the figure. Furthermore, the output data D1 of the selector 35 is supplied to the address terminal. Zoshi"r, 't'
The data in each of the recording areas 36a to 36e designated by output JD1 of the selector 35 is read out in parallel and supplied to the selector 37. Note that the recording area 36a~
Each data in 36e is converted to EFMD-'AD (EFMD
address data), RCIF-AD, WC2F-AD,
They are called DACD-AD and RC2F-AD. selector 3
7 selects the data supplied to each of the input terminals 11 to I5 based on the signals supplied to the select terminals Sel to Se 51\, and outputs the data to the output terminals Q1. It is a circuit that comes out from Q2, and each i is connected to each select terminal Sel~3e5-.
i 1 u signal is supplied to the output terminal) 1. Q
The data outputted from 2 is as shown in the frame marked with the month 378. The adder 38 has its input terminals A and B.
The output of the AND gate 39 is supplied to the carry element C:. The control signal Cl2D is input to one input terminal of the AND gate 39, and the data D is input to the other input terminal.
1 LSB (lowest pitch I; hereinafter referred to as signal CaO) is supplied. Adder 40 is that person)Q child A
, B, and the output of the OR gate 40a is supplied to each key 1/re terminal Ci. Further, the adder 41 is a circuit that adds the data of the input terminals A and 13. The reference counter 42 is an 11-bit pinary counter, and up-runs the signal supplied to its clock terminal CLK. The U/D counter 43 is a 4-bit up/down counter, and counts up the signal supplied to its no-tube terminal U.
In addition, the signal supplied to the down terminal 1] is counted down. This U/1] counter 43 is set to 1-4 in the initial state, and the output to the counter 1 can only take values from 0 to 81. Then, by the adder 41.11% power counter 42, U/D counter 43, switch circuit 44, and inverter 45 described above,
A reference address generation circuit 46 is depicted. Further, reference numeral 15A indicates only a part of the timing control circuit 15 shown in FIG. Next, the operation of this address control circuit 1 will be explained in FIGS.
This will be explained with reference to FIG. (Operation of Address Control Circuit 1) Both FIGS. 15 and 16 are timing charts for explaining the operation of the address control circuit 1. Although this timing chart is shown divided into six columns of timing charts (V-1) in the figure due to space limitations, it is actually a continuous timing chart. For example, the timing O in the second line of Figure 15 is the timing O in the first line of the diagram.
1, timing 4 F3 is connected, and timing O in the first line of FIG. 16 is connected to timing 48 in the third line of FIG. In addition, in the following explanation, d5 is the first
The timings from the first line in FIG. 5 to the third line in FIG. For example, timing 28 in the first line of FIG. 15 is written as timing 1-28. Also,
This timing 1? The time base of -1- is the clock pulse φ. This timing chart shows the processing process for one frame Fr (one frame processing i1j recycle). That is, all processes such as symbol write processing, C1, C2 data, 1) ΔC output, etc. in one frame Fr are performed during 49X6=294 timings shown in this figure. FIG. 17 is a diagram C showing each relative area of the RAM 6 in the same manner as in FIG. 11 described above. As shown in this figure,
The RAM 6 has 32 relative areas in which symbols WO to P3 are respectively written, and 01. The relative area (two columns on the right in FIG. 17) in which two flags are inserted into J1 is designated as A1. In this case, the relative area in which the CI and C2 flags are written consists of the 109 area in which the 01 flag is written, the 18 area in which the 02 flag is written, and the IT 135 area, which is 8 areas for jitter absorption. Further, the relative areas in which the symbols WO, W1...P3 are written are 119.11'6. ...consists of 11 areas. Here, for example, the reason why the relative area in which the symbol WO is written is the 119 area is that the 109 area is used to process the delay of 108 delay times, 1 area is used for symbol writing, and 1 area is used for the 1 = 1 of the DAC output. This is because eight areas are required and eight areas are provided for jitter absorption. The operation of the address control circuit 1 shown in FIG. 12 will be explained below. First, the reference address generation circuit 46 will be explained. First, the control signal EFMD supplied to the switch circuit 44
As shown in FIG. 15.16, η occurs regularly at approximately every four timings. And this control signal E F M
At the timing when D becomes the ``1'' signal, the address for writing the symbol from the buffer 4 to the RAM 6 is output, and at other timings, C enters the symbol processing 1 (data input/output with AM6 and The address for reading the output data to the DAC from the RAM 6 is output. When the control signal E F tvl D becomes the "1" signal, the switch circuit 44 becomes open, and the UZD
The output of the counter 43 is supplied to the input terminal A of the adder 41. As a result, from adder 41 to U/D card jitter 43
The sum of the output data UDD and the output data BD of the reference counter 42 (UDI) +13D is output, and therefore, the data UDD +13D is output from the inverter /'I5.
is output, and this data (month) D to BD is supplied to the input terminal A of the adder 40 via the reference address EADR mentioned above. On the other hand, when control signal 8 [FMD is “O” signal,
The output data ADO of adder 41 becomes data BD,
Then, the output of the inverter 45 becomes data BD, and this data B1) becomes the reference address M A mentioned above.
l) R is output to the adder 40. Here, each state of change of the reference addresses EADR and MADR will be explained assuming that the reference counter 42 is 4 bits to 1 (actually 11 bits). First, the switch circuit 44
When is A (symbol processing, reading output data to DAC>, output data Bl of the reference counter 42) changes as shown in column (a) of Table 1, the reference address MADR (=81)) changes as shown in the doujin (b) column. That is, the reference address M ADR changes to an address one address younger each time the reference counter 42 is incremented. Next, when the switch circuit 44 is in the open state (symbol writing), the U/D counter 43
If the output data UDD of the adder 4 is 14'', as the output data BD of the reference counter 42 changes, the output data BD of the adder 4 is
The output data △D○ of 1 changes as shown in Table 1 (C) column, and as a result, the reference address EADR changes as shown in Table 1 (C).
D) Changes as shown in column. 1, the reference address E A l) R changes to an address one address younger each time the reference counter 42 is incremented, and always becomes an address younger by the value of the data UDD than the reference address MADR. Table 1 (a) BD O123A 5 6 7 B 9 10
1+ 12 13 14 45 Next, reference counter 4
2 is incremented from 1 to 2 by the internal frame synchronization signal XFSYNC created in the timing control circuit 15△.
be done. This internal frame synchronization signal XFSYN
As is clear from Figure 15.16, C occurs at the end of one frame processing cycle (strictly speaking, at timing 6-46).In other words, the output data BD of the reference counter 42 is generated at the end of one frame processing cycle. 83 within the range and does not change (except for timing 6-47.48), so,
The reference address MADR also does not change. On the other hand, the LJ/D counter 43 is incremented by 1 by the LFM frame synchronization signal VFSYNC, and decremented by the internal frame synchronization signal X Fs Y N C. Here, as mentioned above, the synchronization signals VFSYNC and XFSYNC are synchronized with each other and d3
Therefore, the EFM frame synchronization signal VFSYN
C typically occurs in the middle of one frame processing cycle. And this EFM frame synchronization signal VFSY
When NC occurs, data LJ1)D increases by "1", and therefore, the reference address EADR changes to an address one address younger. Next, the internal frame synchronization signal
When YNC is output, the data UDD goes down by "1", but at this time the output data BO of the depletion counter goes up by "11", so the reference address EADR does not change. As mentioned above, the reference address MADR changes to an address one address younger each time the internal frame synchronization signal XFSYNC is output, and the reference address LADR changes to an address one address younger each time the LFM frame synchronization signal VFSYNC is output. Change. Next, the address control operation performed in this address control circuit 1 will be described in detail. (1) RAM of symbols in symbol write control buffer register 4 (Fig. 4)
As mentioned above, writing to the 17th area is performed at the timing when the control signal EFMD shown in FIG.
] - rear at the top of each relative area except for the relative area for flag writing in the figure. First, when the EFM frame synchronization signal VFSYNC is output from the receiving circuit 2 shown in FIG. 4 and supplied to the EFM symbol counter 33 shown in FIG. 14. In this state, the control signal E'F M D
When the "'1" signal rises, the "1"1" signal is supplied to the select terminal Se4 of the selector 35, and as a result, the EF~
The output data "0" of the 1-symbol counter 33 is supplied to the ROM 36 via the selector 35, and the data i'-(14th
(see figure) are supplied to input terminals 11 to I5 of the selector 37, respectively. At this time, the select terminal Se5 of the selector 37
The "1" signal of the signal EFMD is supplied to the EFMD. As a result, as shown in the frame with reference numeral 37a, data from the input terminal 11 is transferred from the output terminal Q1 of the selector 37,
That is, data "135" in address 0 of the storage area 36a of the ROM 36 is output, and rOJ is output from the output terminal Q2. Also, at this time, the control signal Cl2D supplied to one input terminal of the AND gate 39 is
As is clear from Figure 5.16, there is a 1101+ signal,
Therefore, the output of AND gate 39 is 110 I+ times the signal. As a result, data N35J is output from the adder 38 and supplied to the input terminal B of the adder 40 as the relative address RΔDR. At this time, the control signals of both input terminals of the A-no-game 1-408 are both at the ``0'' signal (Figure 15.1G), so the data EADR+RADR=
FADR+135 is output and supplied to the RAM 6 as an address signal ADS. In this way, the first control f31 F M l) (“1
At the timing of ``''), the address EADR+135 is output from the adder 40 to the RAM 6. On the other hand,
At the timing of the first control signal EFMD ("1") described above, the third stage buffer 4. When the symbol WO has already been input to the data bus DABSI (Fig. 4) at the timing of the signal EFMD (“1”), the symbol W is input to the data bus DABSI (Fig. 4).
o is output, and a control signal WE (“1” signal) is also supplied to the read/write control terminal R/W of the RAM 6. As a result, symbol WO is written to address EADR+135 of RA IVI 6. At the same time, the control signal V S Y M B is sent from the write control circuit 5.
is output and supplied to the increment 1 terminal ING of the EFM symbol counter 33, and as a result, data [-1] is output from the M symbol counter 33 at the timing of the next clock pulse φ. On the other hand, if the symbol WO has not yet been input into the third stage buffer 4e of the buffer register 4 at the timing of the first control signal EFMD shown in (above),
Neither the control signals WIE nor VSYMB are output, and therefore neither the RAM 6 nor the EFM symbol counter 33 is incremented by 1-. In this case, at the timing of the next control signal EFMD (“1”), the address E A D R-1 is sent from the adder 40 again.
-135 is output. Note that the fact that the address E A D R-+-135 indicates the top area of the relative area for symbol writing in FIG. 17 means that the number of areas ('+35 ) it should be clear. Next, when the symbol WO is imported and the output data of the EFM symbol counter 33 becomes f'IJ, when the timing of the control signal EFMD ("1) comes again, the ROM 36 The data r254J in address 1 of the storage area 36a is the relative address R.
The address EADR+254 is supplied to the adder 40 as ADR, and as a result, the address EADR+254 is outputted from the adder 40 to the RAM 6. At this time, if the symbol W1 is manually input to the third stage buffer 4e of the buffer register 4,
The same symbol W1 is address EADR+2 of RAM 6
19 in 54. Here, 254=135+11'
9 and r 119 J is the number of the relative area for symbol WO shown in FIG. This is the address of the top area of the area. Thereafter, the above-mentioned overpass is repeated, and as a result, RA
M6 symbol writing is performed. Incidentally, as is clear from the above description and as shown in 4, the address ADS output from the AC-40 at the time of writing this symbol is expressed by the following equation. ADS=EADR+EFMD-AD(xl)--
- (1) Here, EFMD-AD (x 1 ) is x1 of the storage area 36a of the ROM 36? H means EFMD-AD in the area. Moreover, x1 is EFM Shinei Cal counter 33 force data. (2) Symbol reading system 11 during 01 decoding is shown in real $I'a in FIG. 17, as is clear when considering the delay section Dly4 shown in FIG. This is done by reading the symbols within the area. Moreover, reading of the symbol in this C1 decoding is performed at the timing of the control signal sequence CISCl5Y "'1" shown in FIG. 15. At the timing when the control signal CISCl5Y becomes the "1" signal, the "1" signal is supplied to the select terminal S02 of the selector 35, and as a result, from the selector 35,
The output data of the CI/C2 symbol counter 32 is output as data D1. Further, a “1” signal is supplied to the select terminal Se5 of the selector 37, and as a result, the relative area 36 of the ROM 36
EFMD 80 in a outputs data [O
-1 is output from the output terminal Q2. Further, the signal Cl2D becomes the "'1" signal, and therefore the signal CaO is supplied to the carry terminal Ci of the adder 38 via the AND gate 39.Roughly, the signal CI2
Since 0 becomes a ``1'' signal, 1'' is supplied to the key 17 terminal Ci of the adder 40. First, at timing 1-3 shown in FIG. circuit 1
5A, the CI/C2 symbol counter 32 is reset, and data rOJ is output from the counter 32.
is output. Next, when the control signal C1C15Y becomes a ""1" signal at timing 1-4, the !ROM3G
"0" is supplied as data 1] 1, and therefore,
Data “135J (1
114) is output and supplied to the input terminal of the adder 38. This [, Y1 signal CaO is "o" and therefore relative address RA I) from adder 38)
r 135 j is output as R, and address M A D R + 135-1 is output from this adder 40.
-1 is output. And this address MADR+1
By supplying 35+1 to RAM6, RAM6
, indicated by the solid line 1a - [symbol W in the rear
O is read and loaded into the data error detection and correction circuit 8. Next, at the falling edge of timing 1-4, 01/C
Data "1" is output from the 2-symbol counter 32. As a result, at the next timing 1-5, r254J is output from the output terminal Q1 of the selector 37, "1" is output from the AND gate 39, and as a result, data r254 + 1 J is output from the adder 38. output, adder/l. The address MADR+254+1+1 is output from the address MADR+254+1+1. This is the solid line of RAM6! The symbol W1 in the area indicated by a is read out. Thereafter, at the timing when the control signal CICl5Y becomes 1'', the above operation is repeated, thereby sequentially reading out the 32 symbols necessary for C1 decoding. The reason why the signal CaQ is added to ci is that it is necessary to shift the symbol readout position by 11 rea to one symbol 1ij, as shown by the solid line 1a in FIG. 17, corresponding to the delay section Dly4 in FIG. In addition, the carry terminal C1 of the adder 40
The reason for adding the ``1'' signal is this ``1'''1''
'If the signal is in the original readout area, 1 area l2 (
This is because the symbols in the area (in the figure ffi17) are read out. Further, the address ADS in this case is expressed by the following equation. ΔDS = MADR + EFMD - AD (: to 2) + Ca
Q+l...(2) However, X2: Output data of C1/C2 symbol counter Here, d3 is generated during C1 decoding.Operations of data error detection/correction circuit 8 and error flag determination circuit 10 in FIG. Explain briefly. First, as shown in FIG. 15, the data error detection/correction circuit 8 detects stoppage, single error detection, double error detection, and double error detection for the syndromes SO to S3 during periods TM1-1 to TM1-5, respectively. Correction, single-error correction. When a single error or a double error is determined, error flags EO, E1 . E2. NE2 is output to error detection circuit 10, and 1c timing 3
-33. Data k indicating the position of the error symbol at timing 3-36, data 1 indicating the position of the error symbol at timing 3-41, and data 1 indicating the position of the error symbol at timing 3-4.
5. At 3-48, data j indicating the position of the error symbol is outputted to the address control circuit 1 (see the timing of the control signal C1C shown in FIG. 15). On the other hand, the error flag determination circuit 10 includes a data error detection/correction circuit 8.
The above error flag IEO-E2. NE2
Based on this, create the 01 flag and set the timing 3-22 (
output to the data bus DABS1 at the reference numeral wcit2). (3) CI flag occupancy write control The 01 flag is written at the above-mentioned timing 3-22 in the area marked with the symbol FO in FIG. 17, that is, the area indicated by the reference address MADR. That is, at timing 3-22, each control signal supplied to the select l-076 children Se1 to Se5 of the selector 37 becomes II O++, and therefore each control signal supplied to the output terminals Se, 1 to Se5 of the selector 37 Both of the control signals become "0", so that the output terminals Q1 . l-OJ is output from each Q2. At this time, the output of the AND gate 39 is also “O”.
′′. As a result, from the adder 38 to the relative address R
"0" is output as ADR. Well, at this timing 3-22, the output of the OR gate 40a is also l.
As a result, at timing 3-22, the reference address MADR is output from the adder 40 and supplied to the RAM 6. In this way, the 01 flag is set once in one frame processing cycle ( ) is written. And this C1
As is clear from the fact that the flag writing area is provided at °U'109x, the past 108 frames have been processed υ
The C1 flag created in the cycle is stored and retained, and when the error flag determination circuit 10 creates the C2 flag, 28 01 flags among these 109 01 flags are referenced every frame l-r. Ru. (4) When correcting a CI error, the (pull read/@include control C1 decoding is performed using the symbols in the area indicated by the solid line 1a in FIG. 17 as described above).
If an error is detected, the error symbol is first stored in RAM.
The data error detection/correction circuit 8 corrects the symbols, and the corrected symbols are written back to the memory 1) in the RAM 6. That is, first, at timing 3-33, the control signal C
When 1C becomes 1'', the select terminal Se of the selector 35
3 is supplied with the "°1" signal, and the data at the input terminal 13 of the selector 35 is outputted from the selector 35 as data D1. Here, at this timing 3-33,
As mentioned above, data I( is output from the data error detection/correction circuit 8 and is supplied to the input terminal 13 of the selector 35. Therefore, at timing 3-33,
Data 1 (is supplied to the ROM 36. Also, at this timing 3-33, a "1'' signal is supplied to the select terminal Se5 of the selector 37. Furthermore, at this timing 3-33, the signal CI
2D is at the ``1'' signal, so (Ca
O (LSB of data) is adder 38's Kirerii☆da;
It is also supplied to the child Ci, and is also supplied to the carry terminal C of the adder 40.
“1” is supplied to ; As a result of the above, the output ADS of the adder 40 at timing 3-33 is ADS=MADR+EFMD・△l) (k) 10C
a O+i...(3) It becomes. And this address △DS is l'< A M
6, the error symbol corresponding to the data I (is read out, and data error detection/Wl' JE
It is supplied to the circuit 8. After these three timings, the data error detection/correction circuit 8 is at timing 3-36.
At the same time, the corrected symbol is outputted to the data bus 1] ABS1, and data k is outputted to the address control circuit 1 again. On the other hand, the control signal C1G becomes 1" again at timing 3-36. As a result, at the same timing 3-36, the address AI)S shown in equation (3) above becomes RA
At the same time, the '1' signal is supplied to read/write control terminal 1 (/W) of RAM6.
As a result, the corrected symbol is written into the original area of the RAM 6. Below, timing 3-41.3-44.3-/15.3
-48, a similar operation is performed at J5, and as a result, data 1. ” correction of the erroneous symbols is performed. (5) Symbol read control during C2 decoding C2 decoding is performed by the delay units Dly4 and D in FIG.
As is clear from consideration of the delay processing of Iy5 and c15G, this is done by reading out the symbols within the area indicated by the broken line 1b in FIG. Further, symbol reading in this C2 decoding is performed at the timing of the control signal C2SC25Y ('1'), which is not shown in FIG. At the timing of this control signal C2C25Y ("1"), 1 is sent to the select terminal S02 of the selector 35.
1111 signal is supplied, and therefore the output data of the C1/C2 symbol counter 32 is supplied to the ROM 36 via the selector 35. In addition, the select terminal Se of the selector 37 4. 111 I+ signals are supplied to each of the output terminals Q1 . Q
2 to F FMD-AL) and RCI F-A respectively
D is output. Furthermore, since the control signal 012D becomes a "1" signal, the signal CaO is supplied to the carry terminal C of the adder 38 via the AND gate 39, and "1" is supplied to the carry terminal of the adder 40. As a result of the above, the control signal C2S Y fvl B becomes "
The address ADS at the timing of 1” is AD
S=MADR+EFtvLD-AD (X 2)+RC
IF-AD (x 2) +Ca O+'+---
-(4) However, X2: C1/C2 symbol counter 32
The output is Then, the CI/C2 symbol counter 32 receives the control signal CI 2SYNC('i''>
After that, the control signal C2C25Y
(“'1”) timing 4-4゜5.6.8.9...
...42, the output data is 0, 1 . ...
...27, and as a result, the broken line 1b in FIG.
Each symbol in the area indicated by is read out. It should be noted that it is clear from the explanation of the above-mentioned item (2) and FIG. 14 that the area indicated by the broken line 1b is addressed by the address ADS shown in equation (4) above. Here, the operations of the data error detection/correction circuit 8 and the error flag determination circuit 10 during C2 decoding will be briefly described. First, the data error detection/correction circuit 8 detects performance 0, single error detection, double error detection, and double error detection of syndromes SO to S3 during periods TM2-1 to TM2-5 shown in FIG. Corrections are made and simple errors are removed. When a single error or double error is detected, error flags EO to E2. NE2 as error flag judgment circuit timing 6=41.44 and timing 6-45.4
6, data 3+ each indicating the error position of the symbol;
j to the address control circuit 1 (see the timing of the control signal C2G in FIG. 16). On the other hand, the error flag determination circuit 10 outputs the C1 flag stored in the RAM 6 and the data error detection/correction circuit 8;
error flags EO to E2. The 02 flag is created based on NE2, and the control signal WC2F (“1”) in FIG.
The data is output to the data node 5 DABS1 at the timing of . (6) 01 Flag Read Control As mentioned above, the error flag determination circuit 10 requires the 01 flag during C2 decoding. Therefore, following symbol reading for C2 decoding as described above,
The C1 flag is read. The 01 flags required during this C2 decoding are the C1 flags in the areas marked with the symbols FO, F4°F8...F2O3 in FIG. 17, that is, every fourth area, and these Each 01 flag is sequentially read out at the timing of the control signal RC1F ('"1") shown in FIG. 16 and input to the error flag determination circuit 10. At the timing of the control signal RC1F (“1”) described above, a “1” signal is supplied to the select terminal Se2 of the selector 35 and the select terminal Se4 of the selector 37, respectively. Further, the control signal C supplied to the AND gate 39
Control signal CI supplied to 12D1 OR gate 4Qa
20. Both DACDs are at the "'0" signal. As a result, the address ADS is ADS=MAI)R−+−RCIF−AD(x 2
)...(5) Then, the C1/C2 symbol counter 32 is
At timing 5-3, the control signal Cl2SYNC("
1'''), and thereafter the control signal RC1F
('“1'') timing 5-4゜5.6,8.9
...42, the output data is 0, 1 .・
...27, and as a result, each C1 flag is sequentially read out (see FIG. 14). (7) The C2 flag write control error flag determination circuit 10 creates a C2 flag corresponding to each of the symbols WO to W23 to be output to the DAC, and converts the created C2 flag (1 bit) into six data (hereinafter referred to as (referred to as 1st to 67th lag data) and output to data bus DABS1. In this case, the 17th lag data includes symbols WO, W1 . W6. C2 corresponding to W7
The 27th lag data is composed of flags, symbols W12, Wl3 . Wl8. The 37th lag data is composed of the C2 flag corresponding to Wl9, and the 37th lag data is the symbol W2.
W3. ．． W8. It is composed of the 02 flag corresponding to W9, and the fourth flag data is the symbol W14. Wl 5.
The 57th lag data is composed of the C2 flag corresponding to W2O and W21, and the 57th lag data is the symbol W4. W5. W10. W
Consists of C2 flags corresponding to l 1 and 1
=, the sixth flag data is symbol W16. Wl 7.
W22. It is configured by the 02 flag corresponding to W2B. Note that the reason for configuring each 7-lag data in this way will be explained later. These 1st to 67th lag data are each at timing 6-16.17°18.2'0
,21.22 (Zunawara, control signal WC2F ("
1”), the data bus D is
It is output to ABSI, and the symbols FO1, FO2,
FO3, FO4, FO5,' are sequentially written in the areas indicated with F2O. Here, the area for writing the 02 flag will be explained. This C2 flag capture area is shown in Figure 17.
It consists of 18 areas from -01 to F36. These areas are divided into six relative areas 5EFO-3EF5 as shown in Figure 18 (same paper as Figure 13).
The first
~67th lag data is written. In this case, phase blockade 1
ii! The reason why 5EFO, 5EF2, and 5EF4 each have 21 areas is that one area is provided for writing and one area for reading output data to AC. On the other hand, the relative areas 5EFI, 5EF3, and 5EF5 are each 4
The reason for this area is the delay section DI shown in Figure 2.
This is because it is necessary to perform the 2-day delay time Takunobu process for y6 also for the C22 lag. That is, relative area 5E
FO,5I=F2.5The C2 flags of the first, third, and fifth nolag data respectively written in EF4 correspond to symbols for which no two-day delay time delay is performed, while the relative area 5
EF1,5EF3. The C2 flags of the second, fourth, and 67th lag data respectively written in SE 5 correspond to symbols delayed by two delay times. Now, the explanation returns to the 02 flag write control. As mentioned above, the first to 67th lag data are each controlled by the control signal WC2F.
(“1”) data bus DABS1
Therefore, writing of these flag data is performed at the timing of this control signal WC2F<"1"). When the control signal WC2F is received as “1”1”, the selector 35
Select terminal Se2 of selector 37, select terminal S of selector 37
A "1" signal is supplied to each c3. Also, at this time, both the control signals C12D and DACD are in the ""O" signal. As a result, the address ADS is as follows: ADS=MΔ1.')R-1-WC2F・AD (x
2>-...(6) Then, the C1/C2 symbol counter 32 is
It is reset by the C control signal Cl2SYNC at timing 6-3, and thereafter the control signal WC2F (" 1
” ) timing 6-16.17゜18.20,21
．． At 22, the output data is 0.1...5
As a result, the 1st to 67th lag data are sequentially written to the C2 flag write area 1 at the above timing (see FIG. 14). (8) Read/write control of 113k when correcting C2 error This read/write control is performed by control signal 02G (" 1
"). At the timing of this control signal 02C ("1"), "1"1 is sent to the select terminal Se3 of the selector 35 and the select terminals S'e3.Se5 of the selector 37, respectively. ″
information is provided. Also, at this timing, the control signal C
I believe that I2D is ``1''1''. As a result, address AD
S is △ DS=MADR+E FMD −AD (k, l
. j)+RCIF-AD(k,l,'j>+C
a O+1 (7) Not shown in equation (7), error symbols are read out and corrected symbols are written based on the address ADS. Note that this address control operation is described in (4) above.
) The operation is almost the same as that in section ), and detailed explanation will be omitted. (9) Read control of 02 flag and DAC output symbol Symbol WO-W23 for which C1 and C2 decoding has been completed
is read from RAM 6 along with the 02 flag and the DAC
Output to. In this case, reading the 02 flag is the 15th flag.
At the timing of the control signal RC2F ("1") shown in FIG. Both the flag and the DAC output symbol are read out based on the output data Do of the DAC symbol counter 31.The DAC symbol counter 31 is configured to read the internal frame synchronization signal output at the end of the previous frame processing cycle. It is reset by the signal XFSYNC, and thereafter the control signal RC2F ('“1
''> and DACD ("1"') timings, timing 1-0.1, 2゜25.26, timing 2-0.1, 2.25゜26, ..., timing (At 3-0, 1, 2, 25°26, the output data DO changes to 0.1.2...29. Then, address control is performed based on the change in output data 1]0. Hereinafter, the reading of the 02 flag will be explained first.The reading of the 02 flag is performed in the area where 13.F34.F15 and F36 are added to F11.F32. This is performed by sequentially reading out the 1st to 67th lag data at timings 1-0.2-0...6-0. That is, control signal RC2F: ("1" ), the select terminal S0 of the selector 35
1 and select terminal 801 of selector 37, respectively II
I II times signal is supplied, and control No. 13 c12D
, DACD are both on the OI+ signal. As a result, the address ADS is: AD'S = MADR + RC2F-AI) (X 3) ・
...(8) However, X 3: This is the exit point of ROM34. However, timing 1-0.2-0...6-
When the output data Do of the DAC symbol counter 3'1 reaches 0.5, 10.15, and 20.25 in 〇, data is stored in the ROM 34 corresponding to each data Do as shown in FIG. evening. , 1゜2.3.4.5 are output in sequence, and (7) the address ADS of equation (8) is determined based on the output data of the ROM 34 (see Figure 14), and the flag data (C2 flag) is read out. Next, reading out the DAC output symbol will be explained. This reading of the DAC output horn symbols is carried out by not reading out the symbols in each area shown by the dotted chain 1ife in FIG. Among these areas, the area where symbols that do not require the delay processing of the starting unit 1) lV6 (not shown in FIG. 2) is stored is one area below the readout area of the C2 decode IL1 (in FIG. ), and the area where symbols requiring delay processing are stored is the area three areas below the read 1 rear during C2 decoding. At the timing of the control signal DACD ('"1"), the selector 35's select t" l) f'a child S01 and the selector 37's selector 1 terminal Se 2. Se 5
A control signal Cl2D is supplied to each terminal, and a control signal Cl2D
is 0'', the output of the AND gate 39 is ``O''
'' signal, and the output of the OR gate 40a becomes ll
I II times the signal. As a result, the address ADS is: ADS=MADR+EFMD-AI)(x 3) 10D
ACD −AD (× 3 )+1−·−(9). Then, the timing of the control signal DACD (“1”), that is, the timing 1-1.2, 25°26.2
-1.2.25,26.・・・・・・6-1.2゜25
．． 26, the output data Do of the DAC symbol counter 31 is 1.2, 3, . /l, (3°7.8,9,
11. . . .29, correspondingly, the J data o shown in FIG. 13 is transferred from the ROM 34 to
．． 7.16. 17. 22.23°・・・・・・2
7 are output respectively. Here, the output of the ROM 34 is 0.
1.2... The reason why the data does not increase sequentially is because the cross section 010S2 shown in FIG. 2 is replaced. That is, RAM 6 has the first
As shown in Figure 7 - J, sea urchin, each symbol is WO...W
They are stored in the order of 23. However, this order is not the correct order of the symbols (the leftmost order in FIG. 1). Therefore, when outputting the DAC, it is necessary to read each symbol in the original correct order.
M D・AD and DΔCl)・AD are read from ROM2O, and JJ is added to each read address data.
Then, an address ADS is formed, and based on this address data ADS, each symbol within the area indicated by the dashed line IC in FIG. 17 is sequentially read out. Here, D
Of course, the 6 values of ACD-AD are 1c values in consideration of the delay processing of the delay unit Dlye in FIG. The reason why the first and 67th lag data have the above-mentioned configurations is that the C
This is to store the two flags in the RAM 6 in the same order as the readout order of the DAC output symbols. The details of the address control circuit 1 shown in FIG. 12 have been described above. For reference, the EFM frame synchronization signal VFSYNC
internal frame synchronization signal XF
'5YNC if it precedes by 4 frames (jitter is +
4), and conversely, the state of R A and M 6 in the case of a delay of 4 frames (when the jitter is -4) is
Not shown in Figure 1, ar 20. In addition, in FIG. 20, the reference address EADR and the reference address MADR (6) match and there is -C, but when writing the symbol, +l I IT is not applied to the carry terminal of the adder 40,
On the other hand, during C1 and C2 decoding and DAC output, l
Since -I IT is applied, processing such as C1 decoding is not performed using symbols in the area being written. As described in detail above, according to the present invention, a memory including a reference address output means for outputting a reference address, a memory storing a plurality of address data, a plurality of counters for controlling readout of the memory, and a memory for storing a plurality of address data. a first selection means for selectively supplying the output of the counter to the memory; a second selection means for selectively outputting the address data read from the memory; and each output of the second selection means. a first addition means for adding the output of this addition means and said l;! Pre-71~
Since the address control circuit is constructed from the second addition means that modulates the output of the address output means, there is an advantage that the address control circuit can be constructed with a minimum amount of hardware. It will be done.

[Brief explanation of drawings]

FIGS. 1 and 2 respectively show a write circuit for writing data to a disk and a process for processing data read from the disk in a CD (compact disk) system. I! FIG. 3 is a schematic diagram showing a state in which data is written to a disc, and FIG. 4 is a block diagram showing the configuration of the main parts of a CD player to which an embodiment of the present invention is applied. , FIG. 5 is a block diagram showing the configuration of the buffer register 4 and write control circuit 5 that are supplied to the CD player V.
FIG. 6 is a timing chart for explaining the operation of the circuit shown in FIG. 5, and FIGS. 7 to 11 each show the basic concept of address control performed by the address control circuit 1 according to an embodiment of the present invention. 7 is a diagram showing the recording state of disk data in the model explanation, FIG. 8 is a diagram showing the basic configuration of the address control circuit 1, and FIG. (A) to (D) are diagrams each showing the data storage state of RAM 6 in the model explanation, and FIG. 10 is a relative area S not shown in FIGS. 9 (A) to (D).
Diagram showing EO to SE3 vertically and separately, 1st
1 is a diagram showing a state in which jitter absorption areas are provided in each of the relative regions SEO to SE3 shown in FIG. 10, and FIG. 13 and 14 are block diagrams showing the configuration of the address control circuit 1, respectively. 17 is a diagram showing the data storage state of the RAM 6 in the normal state (jitter O), FIG. 18 is a diagram showing the storage area for writing the C2 flag in the RAM 6, and FIGS. In Figure 20, the jitter is +4. 31...Counter (DAC symbol counter)
, 32...Counter (C1/C2 symbol counter), 33...NoJ counter ([EFM symbol counter), 35...First selection means (hirefter) , 36...Memory (ROM), 37...
...Second selection means (selector), 38...
- First addition means (adder), 40... second addition means (adder). Applicant Nippon Gakki Mfg. Co., Ltd. - Figure 13 r1n Patent Application No. 186104 of 1986 20 Name of Invention Address control circuit in DAD player 3 Person making correction Patent applicant (G07) Nippon Gakki Mfg. Co., Ltd. 4 The details of the "Detailed Description of the Invention" in the agent's memorandum, and the drawings and sheets. Exit 1: The next part that should have been marked a is supplemented as shown below. Ru0 Koki-i Ko41

Claims (1)

[Claims] (a) Reference address output means for outputting an I quasi-address; (b) ? a memory in which U number of address data are stored in advance; (C) a plurality of counters that are set in accordance with the mode of address control and that control reading of the address data in the memory; (d) the plurality of counters; (0) a second selection means for selectively outputting a plurality of address data read from the memory; (f) Said second
(0) a reference address outputted from the reference address output means; and (0) a reference address output from the reference address output means; An address control circuit in a DAD brake X7, comprising: second caulking means for adding relative addresses output from the DAD brake X7.