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JPS6077421A - Alignment pattern - Google Patents

Alignment pattern

Info

Publication number
JPS6077421A
JPS6077421A JP58186150A JP18615083A JPS6077421A JP S6077421 A JPS6077421 A JP S6077421A JP 58186150 A JP58186150 A JP 58186150A JP 18615083 A JP18615083 A JP 18615083A JP S6077421 A JPS6077421 A JP S6077421A
Authority
JP
Japan
Prior art keywords
alignment
pattern
mask
pattern image
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58186150A
Other languages
Japanese (ja)
Other versions
JPH0144009B2 (en
Inventor
Hitoshi Hoshino
仁 星野
Tsuneo Funatsu
船津 恒雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58186150A priority Critical patent/JPS6077421A/en
Publication of JPS6077421A publication Critical patent/JPS6077421A/en
Publication of JPH0144009B2 publication Critical patent/JPH0144009B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To generate general purpose alignment pattern and transfer it with high accuracy by providing, in the side of mask, the contour figure wherein the L-shaped patterns in different sizes are arranged proportionally and symmetrically. CONSTITUTION:A plurality of contour figures 12 are sequentially formed proportionally and symmetrically to the internal circumference from the external circumference with the scaling and then apertures are formed. Thereby, a pattern image 11 for alignment of masks 1 formed like a letter L. This shape corresponds to the pattern image for alignment of substrate 2 formed in different size indicated by the dotted line and alignment can be realized easily at a high speed. When the pattern image 14 where apertures 15 are radially formed is used, the overlapped pattern portions are reduced, making easier the alignment.

Description

【発明の詳細な説明】 (a)発明の技術分野 本発明はフォトリソグラフィ技術に於ける一括露光法に
係り、特にマスク又はレチクルに形成される位置合せ用
のパターン形状に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a batch exposure method in photolithography technology, and particularly to a pattern shape for alignment formed on a mask or a reticle.

(b) 技術の背景 微細加工技術の発展に伴い超LSI分野では、1.2〜
1.5μのケート幅の微細加工が要請されている。従来
のフォトI+ソグラフィ(光旗光)技術では充分な対応
が不可能で高精度化した等倍プロ装置、縮小型プロジェ
クションアライナ等を又互に組合せて転写する混合アラ
イナ方式が用いられる。例えば縮小投影結党装置では通
常10:1の縮小率でレチクル上のパターンをステップ
アンドリピート(Step and Repeat) 
方式でチップ毎にワンショットづ\投影露光するため精
密な画像転写がoJ能となる反面スルーブツトはかなり
の時間を要する。このため高精度を要するパターン転写
にはこの方式が最適であり、あまり精度を要しないバタ
ーニングにはコンタクトアライナ又は等倍に結像するプ
ロジェクションアライナを用い処理効率を高める混合露
光法が一般的に用いられる。何れの方法もマスク又はレ
チクル上に精密描画した微細パターンをウェハ上に転写
するため位置合せは京4)な課題である。
(b) Technology background With the development of microfabrication technology, in the VLSI field, 1.2~
Microfabrication with a cage width of 1.5μ is required. Conventional photo I + lithography (optical flag light) technology cannot provide sufficient support, so a mixed aligner method is used in which high-precision full-size professional equipment, reduction type projection aligners, etc. are combined with each other for transfer. For example, in a reduction projection forming device, the pattern on the reticle is usually stepped and repeated at a reduction ratio of 10:1.
In this method, projection exposure is performed one shot at a time for each chip, which enables precise image transfer on the OJ, but on the other hand, throughput requires a considerable amount of time. For this reason, this method is optimal for pattern transfer that requires high precision, and for patterning that does not require high precision, a mixed exposure method that increases processing efficiency by using a contact aligner or a projection aligner that forms an image at the same magnification is generally used. used. In either method, a fine pattern precisely drawn on a mask or reticle is transferred onto a wafer, so alignment is a serious problem.

(el 従来技術と問題点 第1図はマスクと半導体基版とを位置合せする状態を示
すための平面図、第2図は第1図における位置合ゼする
従来のパターン画像を示す拡大図第1図においてマスク
1上に精密描画された微細パターンを基板2に転写する
が、マスク1と基鈑2との位置合セにかなりの精度が要
求される。
(el) Prior Art and Problems Figure 1 is a plan view showing the alignment of the mask and semiconductor substrate, and Figure 2 is an enlarged view showing the conventional pattern image aligned in Figure 1. In FIG. 1, a fine pattern precisely drawn on a mask 1 is transferred onto a substrate 2, but considerable precision is required for positioning the mask 1 and the substrate 2.

し0えば微細Ni、@!、を扱って配線層をパターン形
成する場合配線層のパターン幅が1〜2μの微細配線を
行なう等における位置合セは厳しい精度が要求される。
Fine Ni, @! , when patterning a wiring layer, strict precision is required for positioning when performing fine wiring with a pattern width of 1 to 2 μm in the wiring layer.

このためスループット向上を計り、位置合せ精度を得る
ために粗い位置合せと、精密な位置合ゼとを組合せた2
ステップ方式は有効である。
Therefore, in order to improve throughput and obtain alignment accuracy, we combined coarse alignment and precise alignment.
The step method is effective.

通常粗い位置合せにはマスク1及び基板2の中心及び周
辺部にモニタチップ3を設け、このモニタチップ3に図
示するような特殊なパターン像3′を描画し、このパタ
ーン像を重ね合せる。次いで精密な位置合ゼには左右対
称位置に設けた斜線で示す位置合せ用チップ4に描画し
たパターン画像を重ね合せてマスク1と基板2との位置
合ゼを行ない顕微鏡により精密修正して位置合ゼしたあ
と一括露光により精度の高いパターン転写が可能となる
。第2図は位置合せパターンを重ね合せて精留位置合ゼ
する具体例をかすものでマスク上の位置合ゼ用チップ4
に胴線で示す輪郭図形を描画したパターン画像5と基板
上に設けた位置合上用パターン画像6との位置合セそ行
なう。
Usually, for rough alignment, a monitor chip 3 is provided at the center and periphery of the mask 1 and substrate 2, a special pattern image 3' as shown in the figure is drawn on this monitor chip 3, and these pattern images are superimposed. Next, for precise positioning, the pattern images drawn on the alignment chips 4 shown by diagonal lines provided at left-right symmetrical positions are superimposed to align the mask 1 and the substrate 2, and the position is precisely corrected using a microscope. Highly accurate pattern transfer is possible by batch exposure after combining. Figure 2 shows a specific example of rectifying position alignment by overlapping alignment patterns, and shows the position alignment chip 4 on the mask.
The pattern image 5 in which the outline figure shown by the body line is drawn is aligned with the alignment pattern image 6 provided on the substrate.

この場合形成されるパターン画像は同一図形であり、4
fli上のパターン画像6に比しマスク上のパターン画
像を比しマスク上のパターンllTi1像を比例対称的
に小形化し、前述したモニタチップを重ね合せ粗い位置
合せによって図に示すようなパターン画像の屹置図が得
られる。この画像間の位置を顕#鏡で目視により補正す
るもので即ちパターン画像のエッヂ(マスク側ンから基
板上のパターンまでの距離例えばa=b、c=dとlる
よう修正することにより尚精度の1XL匝合せがE]能
である。
In this case, the pattern images formed are of the same shape, and 4
Comparing the pattern image 6 on the mask with the pattern image 6 on the fli, the pattern llTi1 image on the mask is proportionally and symmetrically reduced in size, and the above-mentioned monitor chip is superimposed and coarsely aligned to create a pattern image as shown in the figure. A map of the location can be obtained. The position between these images is corrected visually using a microscope, that is, by correcting the edge of the pattern image (the distance from the mask side to the pattern on the substrate, for example, a = b, c = d). Accurate 1XL fitting is possible.

しかしマスク側に形成するパターン1ilii像5は基
板上に形成するパターンIIjIl保6の大きさVCよ
って規定されることになり汎用性が得られない。例えば
基板背面に分離構造の拡散層を形成し反転して基板主面
を研磨して′a極影形成る防霜1体分離構造の電極配線
層のパターン形成では、この位置合せパターンの大きさ
が途中工程の研Hにより変化し、マスク側の位置合せパ
ターンでは対応できないことが屡々発生する。間隔が狭
すぎたり開きすぎにより目視誤差を生ずる。或いはit
、 fzり合りて見かけ上の位14合せとなり微細修正
が不可能となる。
However, the pattern 1ilii image 5 formed on the mask side is defined by the size VC of the pattern IIjIl 6 formed on the substrate, so that versatility cannot be obtained. For example, in patterning an electrode wiring layer of a frost-proof one-body separation structure, in which a diffusion layer with a separation structure is formed on the back surface of the substrate, the main surface of the substrate is reversed and polished to form a polar shadow, the size of the alignment pattern is It often happens that the position changes due to the polishing process in the middle of the process and cannot be handled by the alignment pattern on the mask side. Visual errors may occur if the spacing is too narrow or too wide. Or it
, fz will match, resulting in an apparent match of 14, making fine correction impossible.

(dl 発明の目的 本発明は上記の点に鑑み汎用性のあるマスク側の位置合
せ用パターンを提供し、基徹上に高精度の回路パターン
を転写jtJ成さゼることを目的とする。
Purpose of the Invention In view of the above, an object of the present invention is to provide a versatile mask-side alignment pattern and to transfer a highly accurate circuit pattern onto a substrate.

(e) 発明の構成 上記1的は本発明によれば試料上に転写すべき被転写パ
ターンを有するマスクと該試料とを位置合ゼするための
該マスク側のパターンが異なる大きざのL字形を比例対
称的に配した輪郭図形で形成されることによって達せら
れる。
(e) Structure of the Invention According to the present invention, the pattern on the mask side for aligning the mask having the transferred pattern to be transferred onto the sample and the sample is L-shaped with different sizes. This is achieved by forming a contour figure that is arranged proportionally and symmetrically.

(f) 発明の実施例 第3し1は本発明の一実施例である位置合せパターン形
状を示す平面図、第4図は本発明の他の実施例を示す位
置合ゼパターン形状の平面図である。
(f) Embodiment No. 3 of the invention is a plan view showing the alignment pattern shape according to an embodiment of the present invention, and FIG. 4 is a plan view of the alignment pattern shape showing another embodiment of the invention. be.

笛1傳1f千す rろvr a fAtの脳1厘双目税
12t、馴、固九ら内周に向け゛ζ順次比例又1称的に
縮尺形成し且つ開口させてL字形に形成したパターン画
像11であって、具体的形状は例えば1辺のパターン幅
及びパターン間隔をそれぞれ4μにとり外形を約50〜
80μ口とし且つ開口部13を10〜20μとしたもの
である。
Fugu 1F 1F 1F Thousand Roro VR A FAT's brain, two -per -two -percent tax 12T, familiar, and inner circumference ζ ζ ζ ゛ ゛ ゛ ゛ ゛The pattern image 11 has a specific shape, for example, with a pattern width of one side and a pattern interval of 4 μm each, and an outer shape of about 50 μm.
The opening is 80μ and the opening 13 is 10 to 20μ.

このような形状とすることにより点線で示す異なるパタ
ーンサイズで形I戊される基板パターン画像14に対紀
−できることになる。
By adopting such a shape, it is possible to correspond to the substrate pattern image 14 which is cut in a shape I with different pattern sizes shown by dotted lines.

即ち顕微鏡による位1h二合セに際し、最適な条件での
パターン相互の選択ができ荀置合セが従来に比し容易と
なり、位置合せ処理の高速化が期待できる。
That is, when aligning two patterns using a microscope, patterns can be mutually selected under optimal conditions, making alignment easier than before, and faster alignment processing can be expected.

第4図では開口部15を放射状に形成したパターン画像
14を示すもので負なり合うパターン部が減少し、位置
合ゼは更に容易となる。
FIG. 4 shows a pattern image 14 in which openings 15 are formed radially, so that the number of negative pattern parts is reduced, and alignment becomes easier.

(g) 発明の効果 以上詳細に説明したように本発明に示すマスクの位置合
ゼパターン画像とすることにより基板の位置合ゼパター
ン画像の変化に対応でき汎用性を増すとともに高速位置
合上が可能となり一括露光装置のスールプノト向上に効
果がある。
(g) Effects of the Invention As explained in detail above, the mask alignment pattern image according to the present invention can respond to changes in the substrate alignment pattern image, increasing versatility and enabling high-speed alignment. It is effective in improving the output of batch exposure equipment.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はマスクと半導体基板とを位置合ゼする状態を示
すための平面図、第2図は第1図における位置合せする
従来のパターン画像を示す拡大図、第3図は本発明の一
実施例である位置合セパターン形状を示す平面図、第4
図は本発明の他の実施例を示す位置合せパターン形状の
平面図である。 図中、1・・・マスク、2・・・・・・半導体基板、3
・・・・・モニタチップ、4・・・・・・位置合ゼ用テ
ップ、5゜11.14・・・・・・位置合せ用パターン
画像(マスク側)、6・・・・・・パターンi[1ll
IJ!(基板側)、12・・・・・・輪郭図形、13.
15・・・・・・開口部。
FIG. 1 is a plan view showing a state in which a mask and a semiconductor substrate are aligned; FIG. 2 is an enlarged view showing a conventional pattern image for alignment in FIG. 1; and FIG. FIG. 4 is a plan view showing the alignment pattern shape according to the embodiment.
The figure is a plan view of an alignment pattern shape showing another embodiment of the present invention. In the figure, 1...mask, 2... semiconductor substrate, 3
...Monitor chip, 4...Tip for positioning, 5゜11.14...Pattern image for positioning (mask side), 6...Pattern i[1ll
IJ! (board side), 12...contour figure, 13.
15...Opening.

Claims (1)

【特許請求の範囲】[Claims] 試料上に転写すべき被転写パターンを有するマスクと該
試料とを位置合せするための該マスク側のパターンが異
なる大きざのL字形を比例対称的に四隅に配した輪郭図
形で形成されていることを特徴とする位置合せパターン
A pattern on the mask side for aligning a mask having a transferred pattern to be transferred onto a sample and the sample is formed of a contour figure in which L-shapes of different sizes are arranged proportionally and symmetrically at the four corners. An alignment pattern characterized by
JP58186150A 1983-10-05 1983-10-05 Alignment pattern Granted JPS6077421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58186150A JPS6077421A (en) 1983-10-05 1983-10-05 Alignment pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58186150A JPS6077421A (en) 1983-10-05 1983-10-05 Alignment pattern

Publications (2)

Publication Number Publication Date
JPS6077421A true JPS6077421A (en) 1985-05-02
JPH0144009B2 JPH0144009B2 (en) 1989-09-25

Family

ID=16183252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58186150A Granted JPS6077421A (en) 1983-10-05 1983-10-05 Alignment pattern

Country Status (1)

Country Link
JP (1) JPS6077421A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160122A (en) * 1984-01-30 1985-08-21 Rohm Co Ltd Method for alignment of mask
WO1997008588A1 (en) * 1995-08-23 1997-03-06 Micrel, Inc. Mask structure having offset patterns for alignment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208722A (en) * 1983-05-13 1984-11-27 Oki Electric Ind Co Ltd Alignment mark for semiconductor integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208722A (en) * 1983-05-13 1984-11-27 Oki Electric Ind Co Ltd Alignment mark for semiconductor integrated circuit device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160122A (en) * 1984-01-30 1985-08-21 Rohm Co Ltd Method for alignment of mask
JPH023534B2 (en) * 1984-01-30 1990-01-24 Rohm Kk
WO1997008588A1 (en) * 1995-08-23 1997-03-06 Micrel, Inc. Mask structure having offset patterns for alignment
US5747200A (en) * 1995-08-23 1998-05-05 Micrel, Incorporated Mask structure having offset patterns for alignment

Also Published As

Publication number Publication date
JPH0144009B2 (en) 1989-09-25

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