JPS6066539A - Clock signal selecting system - Google Patents

Abstract

PURPOSE:To supply a stable master clock signal with high reliability by detecting an abnormality of the phase of a reference clock signal before it has a considerable influence upon a generated master clock signal and switching this clock signal to a new reference clock signal. CONSTITUTION:In comparison with a selectivity Qe of a resonance circuit for extracting clock components included in a clock extracting circuit 1 of each system, an equivalent Qp of a phase locked oscillator PLO51 included in a master clock generaging circuit 5 is set to a sufficiently higher value. For example, if an abnormal situation such as loss of a transmission signal in the reference side is caused, the speed of phase changed of the master clock signal generated from the oscillator PLO51 is made sufficiently lower than that of the clock signal of the clock extracting circuit 1 in the loss side, and the abnormality of the reference signal is detected by the phase difference between them exceeding a specific threshold, and the reference signal is switched to the reference signal of the other side where no abnormalities are detected in phase difference. Thus, variance of the phase of the master clock signal for the occurrence of an abnormal situation is held down to a minimum.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock signal selection method, particularly to a clock signal selection method in a multi-system synchronization method among digital signal transmission methods.

For example, as shown in FIG. 1, a plurality of systems, for example, the first system to the Nth system (SMS-1 to SYS-N), are connected between the wired section and the wireless section of the digital transmission method.
Assume a system (synchronous system) t- in which transmission signals are exchanged by the system, and the digital signals of these plural systems are mutually synchronized.

That is, for signals transmitted from the wired section side to the wireless section side, multiplexing is performed based on one master clock in the multiplexer on the wired section side, and each transmission of 5M5-1-SMS-H is performed. The signals are mutually synchronized.

On the other hand, in the signal processing device used on the wireless section side, a plurality of clock extraction circuits are installed to extract all of the clock components from these transmission signals. A method is used in which this signal is selected and used as a master clock signal for common control in all signal processing devices.

In this way, the method of making it possible to select one of the multiple clock extraction circuits and using it as the master clock is a method for increasing the reliability of the master clock signal on the signal processing device side. It is clear that this will be a useful tool.

In clock selection schemes for such purposes,
Generally, if the transmission signal of the system currently selected to be used as the master clock signal disappears, it is immediately switched to the output of the clock extraction circuit of another normal system and used as the master clock signal for all master clock signals. However, in conventional systems, when an abnormality is detected and the output is switched to the output of the clock extraction circuit of a normal system, a phase jump occurs in the master clock signal generated in this way, causing transmission problems. It has the disadvantage of having various adverse effects on the system.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an overall clock signal selection method which eliminates the above-mentioned conventional drawbacks.

The method of the present invention is a multi-system signal synchronization method of a digital transmission method, which includes a plurality of tallock signal extraction means biased by a resonant circuit having a specific sharpness that responds to a digital transmission signal or a clock signal, and a plurality of clock signals in front of the resonant circuit. main clock signal generating means which is responsive to one output selected from the outputs of the signal extracting means and is equipped with a resonant circuit having a sharpness higher than that of the resonant circuit; and a phase of the output of the main clock signal generating means. a phase synchronization detection means for detecting all phase synchronization states by matching the phase of the output of each of the clock signal extraction means; and a clock signal supplied to the main tarlock signal generation means based on the output of the phase synchronization detection means. It includes selection means for selecting all outputs of the extraction means.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an entire embodiment of the present invention.

In this embodiment, beam 1 system 5YS-i and second system 5
If two transmission systems of M5-2 exist, gold is shown.

Referring to FIG. 2, this embodiment includes a clock extraction circuit 1-1 and a synchronization detection circuit 2-1 for the first system, and a lock extraction circuit 1 for the second system, which is similar to the above.
-2, a synchronization detection circuit 2-2, a clock selection control circuit 3, a clock switching circuit 4, and a master clock generation circuit 5, all of which are shared by both systems.

Tarock extraction circuit 1 (1-1 and 1-2) of each system
) is the transmission signal 100 (100−
1 and 100-2), a resonant circuit that resonates with the clock frequency and has a specific selectivity (Qe) is constructed.

Further, the synchronization detection circuit 2 (2-1 and 2-2) includes a phase ratio collector 211, a phase coincidence detection counter 22, a NOR gate 23. Holding circuit 24. and a flip knob 25.

The reverse switching circuit 4 includes an impark/buffer 41 and NOR gates 42, 43 and 44, and the master clock generation circuit 5 includes a phase development oscillator (PLO) 51 and a timing generator 52.

As will be described later, in this PLO 51, the isometric selectivity (Qp) determined by its loop bandwidth is the selectivity (Qe) of the resonant circuit included in the clock extraction circuit 1.
Yoshi is also set to be much larger.

Now, the operations of the two embodiments are as follows.

The transmission signal of the first system is transmitted via the line 100-1', and this transmission signal 100-1 is supplied to the clock extraction circuit 1-1, where the clock component is extracted by the above-mentioned resonant circuit. is further shaped into a clock signal having a logic level of b"l"No", and the line 1
The signal is supplied to the synchronization detection circuit 2-1 and the link switching circuit 4 via 01-1'r.

On the other hand, the transmission signal of the second system is transmitted via the line 100-2.
-21C is supplied to the synchronization detection circuit 2-21C, which is shaped into a clock signal in the same manner as described above, and is sent to the synchronization detection circuit 2-2 through the line 101-2'.
2 and the clock switching circuit 4.

Now, the clock switching circuit 4 is the clock selection control circuit 3.
Selection control signal 300? generated by the operation described below.
and thereby the clock signal 1 on the first system side.
91-1. or the clock signal 1 on the second system side
01-2, and supplies it to the masked clock generation circuit 5 via the line 400 (if the output 300 of the circuit 3 is logic "1'l", the clock signal 101-1 on the first system side is selected and also the output 30 of circuit 3
0 is logic l1On, the clock signal 101-2 on the second system side is selected).

The master clock generation circuit 5 locks the phase of all of the supplied clock signals in addition to the internal phase synchronized oscillator PLO51. The output of this phase-locked oscillator PLO51 is shaped by a mapping generator 52.
It is distributed within the system via the line 500 as a master clock signal having a logic level of R□'', and is also supplied to the synchronization detection circuit 2-1, 2-2 and the clock selection control circuit 3.

Now, in a normal state, the master clock signal 500 generated in this way and the clock signals 101-1, 101- extracted from the first system and the second system
2 is set as shown in FIG. 3 (5).

That is, the clock signals 101-1 and 101-2 extracted from the first system and the second system are adjusted to be in phase with each other, whereas the clock signals 101-1 and 101-2 extracted from the first system and the second system are adjusted so that they are in phase with each other. The master clock signals 500f'j, .
The A eye advances by approximately 90 degrees, and the master clock signal is 500.
The rising leading edge of clock signals 101-1 and 10
It is set to be located approximately in the center of the "0" level of 1-2.

Signal 101-1 and signal 50 having such a phase relationship
0 is supplied to the synchronization detection circuit 2-1, but the circuit 2-1
Internally, both are supplied to the D terminal and the tarlock terminal (C terminal) K of a phase comparator 21 constituted by a D-type clip-flop, and as a result, the output side signal 210 of the comparator 21 becomes 1IOI level. is held (see signal 210 in FIG. 3(5)).

This output signal 210 is supplied to the phase coincidence detection counter 22. This counter 22 outputs a logic level "0" through all lines 220 ffi for a certain period of time when the signal 210 continuously maintains the lIO" level for a predetermined number of supplied clock signals 500 or more. The output 210 of the comparator 21 mentioned above and the output 220 of the comparator 21 are applied with 23Vc, and as a result, the above-mentioned state is maintained for a period of more than one mask clock signal 500. Continuing, the output 230 of the NOR gate 23 becomes a logic V-pel constant time ``'1'', and the holding circuit 24 composed of flip-flops is completely reset and the output 240 becomes the logic level noI+.

This is further laminated by a masked clock signal 500 in flip-flop 25 and its output 250-
The logic level "o'r" is output to 1 and is supplied to the all tarlock selection control circuit 3.

Exactly the same process as above is performed in the second system, and the output 250- of the synchronization detection circuit 2-2 of the 27th stem is
A logic level "O1" is outputted to the clock selection control circuit 3.

As described above, when the system is in a normal state, the phase relationship between the generated master clock signal 500 and the extracted clock signals 101-1 and 101-2 of each system is shown in FIG. Fields &l/C having such a preset mutual relationship are detected by the synchronization detection circuit 2-1 of each system.
．． 2-2 has 1. The Toren Novel 10'' is fully output to indicate that it is in a normal synchronized state, and this is supplied to the total tarokk selection control circuit 3.

In this way, when both systems are in a normal synchronous state (both inputs are at the logic V level "0"), the control circuit 3
) at the logical level! 11" is output through all 300 lines, and the first system side selects the gold.(Of course, it goes without saying that all the second system side may be selected.) In this way, under normal operating conditions, Clock signal 10 extracted from @l system by clock extraction circuit 1-1
1-1 is supplied to the master clock generation circuit 50 and the phase synchronized oscillator PLO51 through all the gJ replacement subcircuits 4, and the mask clock 500, which has been filtered out based on all of these, is supplied to the synchronization detection circuits 2-1 and 2-2. , each synchronization detection circuit 2-1
．． 2-2 detects all synchronization states and turns logic level n On
2 clocks are supplied to the selection control circuit 3, whereby the circuit 3 fully selects the first system side and continues its normal operation.

Now, suppose that the currently selected transmission signal 100-1 on the first system side disappears for some reason while such normal operation is being performed.

As mentioned above, the % clock extraction circuit 1-1 has a relatively high selectivity (Qe), so even if the resonant signal to be accommodated disappears, this resonant circuit performs all damped oscillations at its own resonant frequency. , the extracted clock signal 101-1 does not disappear immediately, but its resonant frequency is generally somewhat different from the clock frequency of the transmission signal that was being driven until now, so the clock signal 1oi after the transmission signal disappears. The -i digit 441 deviates from the phase of the same clock signal before the transmission signal disappears at a speed related to this Qe.

On the other hand, the master clock signal 500 is also a signal generated as a reference for all the phases of the clock signal 101-1 whose phase is shifted, so when the phase of this reference signal shifts, the phase shifts accordingly, but the phase synchronization Oscillator PLO5
Isometric Q p ′fcs determined by a loop bandwidth of 1
The QCVc of the resonant circuit included in the extraction circuit 1 should be selected to be much larger than that of the clock signal 101-1.
Compared to the speed of the phase shift of the master clock signal 50
The speed of the zero phase shift can be set to be sufficiently small.

In this way, at a certain point in time after the transmission signal of the first system disappears, the clock signal 101 extracted from the second system, as shown in FIG.
-2 maintains the previous normal phase, whereas the clock signal 101-11 from the first system has a phase lag of nearly 180 degrees with respect to the original correct h phase.
The master clock signal 500 created based on this is adjusted so that the phase lag is kept to a fraction of the original correct phase (in the figure, about one-third, about 60 degrees). I can do it.

In this way, when the phase of the clock signal 101-1 extracted from the first system in which the transmission signal has disappeared suddenly changes from the normal state, the phase change of the master clock signal 5000 generated based on all of this will be as described above. Due to the large difference in Q, I was unable to follow this.

The relative phase difference between the two will change.

As a result of this change, the rising leading edge of the master clock signal 500 changes to a state where the phase comparator 21 of the synchronization detection circuit 2-1 samples the logical level "1" portion of the clock signal 101-1 (the first 3 (I3)), the output 210 of this comparator 21 is inverted from the previous state of logic level n O++ to the state of logic level "1", which is inverted to the output 240 of the holding circuit 24 "1". latches, and furthermore, at the leading edge of the rising edge of the mask clock 500, the flip 70 knob 24? "1" and connects it to the clock selection control circuit 3 through all lines 250-1.
supply to. Thus, the synchronization detection circuit 2i notifies the tv"l"VCL selection control circuit 3 of the occurrence of a synchronization abnormality on the first system side to the logic v of the output 250-1.

On the other hand, in the synchronization detection circuit 2-2 on the 27th stem side, the clock signal 10l-2i' extracted from the transmission signal is
! All the correct phases from before are maintained, and on the other hand, the change in the phase of the master clock signal 500 is small compared to the phase change of the clock signal 101-1 on the first system side, as described above. side logic level “O” to l
Even at the time when the inversion to '1'' occurs, the master clock M
The leading edge of clock signal 500 is still clock signal 10.
1-2 (7) “Refer to Figure 3 for a sample of 0 level)”
, no reversal occurs on the second system side as in the first system side.

As a result, the clock selection control circuit 3 is in an abnormal state (
Report all parties at logical level ``11'').

A notification of the normal state (logical novel "0") is received from the output 250-2 of the synchronization detection circuit 2-2 of the second system.

Accordingly, the multicontrol circuit 3 switches its output from logic level nln to 0'' so as to select the clock signal 101 on the second system side, and the clock switching circuit 4 selects the clock signal 101 on the second system side. -2'r The signal is controlled to be supplied to the master clock generation circuit 5.

Thus, the phase-locked oscillator PLO51 is phase-locked to this new supplied reference signal, so that the mask clock signal 500 is again fully restored to its initial phase-locked state.

As described above, according to this embodiment, the phase synchronized oscillator PL051 included in the master clock generation circuit 5 is How many songs Qpff
For example, if an abnormal situation occurs such as loss of the transmission signal on the reference side, compared to the speed of the phase change of the clock signal of the clock extraction circuit 1 on the loss side,
The oscillator P is phase-synchronized with respect to this clock signal.
By making the speed of phase change of the master clock signal generated from LO51 sufficiently slow, the resulting phase difference between the two exceeds a specific threshold value, and the abnormal phase difference of the reference signal is detected. If the abnormality is not detected at all, switch the reference signal to the other side.

This is intended to minimize the total fluctuation in the phase of the master clock signal when such an abnormal situation occurs.

In the above embodiment, the entire PLO 51 is used in the master clock generation circuit 5, and the flyhole effect thereof is fully utilized, but the sound of a resonant circuit with a high Q'r such as a crystal filter may also be used for this purpose. can.

Further, in this embodiment, the case where there are only two systems, the first system and the second system, has been described, but the same procedure can be performed even when there are a larger number of systems.

In this case, the clock selection control circuit and the clock switching circuit switch and select the clock signal from the clock extraction circuit of the system in which the synchronization detection circuit has not reported an abnormal state according to a predetermined priority order, and use it as a reference signal. What is necessary is to supply it to the master clock generation circuit.

Further, although the tarock frequency of the transmission signal of each system and the frequency of the master clock signal need to be synchronized with each other, they do not necessarily have to be the same frequency.

In this case as well, it can be implemented in almost the same way.

Also, is the synchronization detection circuit 2 used in the above embodiment a one-time exception?
Although shown, the present invention is not limited thereto.

Furthermore, in the first embodiment described above, the synchronization extraction circuit 1 is assumed to receive all the transmission signals, but of course, if the clock signal of the corresponding system can be obtained, this may be used.

As described above, according to the present invention, all normal lock signals are selected from a plurality of extracted clock signals, and all master clock signals are generated as a reference, and if the phase of the reference clock signal is not generated. When the phase of the master clock signal changes by more than a predetermined threshold value, this is detected, and the clock signal that does not undergo such a phase change is switched to be used as a reference.

In the present invention, in contrast to the Q of the resonant circuit for extracting all the reference clock signals, the Q of the circuit for generating all the master clock signals 7. By selecting a sufficiently high value, if an abnormality occurs in the phase of the reference clock signal, this can be completely detected and switched to a new reference clock signal before the effect becomes noticeable on the generated masked clock signal. Even when an abnormality occurs, the phase fluctuation applied to the mask clock signal is maintained to be minimized.

This makes it possible to provide a complete clock signal selection system that provides a highly reliable and stable master clock signal.

[Brief explanation of the drawing]

Fig. 1 is a block diagram for explaining all the connection points between the wired section of the digital transmission method and the wireless section of the digital transmission method, Fig. 2 is a plotter diagram showing one embodiment of the present invention, and Fig. 3 and 4 are the actual implementations. A time chart showing the normal state of the example and FIG. 3(B) are a time chart showing the operation in the abnormal state of this embodiment. In the figure, 1-1.1-2... Clock extraction circuit, 2-1
゜2-2...Synchronization detection circuit, 3...Clock selection control circuit, 4...Clock switching circuit, 5...Master clock generation circuit, 21 ...
... Phase ratio slave, 22 ... Phase coincidence detection counter, 23 ... Noah gate. 24...Holding circuit, 25...Flip-flop, 41...I/harter/buffer, 4
2,43゜44... Noah Gate, 51...
...Phase-locked oscillator (PLO), 52...Timing generator.

Claims (1)

[Claims] In the multi-system signal synchronization method of digital transmission method,
a plurality of clock signal extraction means comprising a resonant circuit having a specific sharpness responsive to a digital transmission signal or a clock signal; and responsive to one output selected from the outputs of the plurality of clock signal extraction means; A resonant circuit with a higher sharpness than the resonant circuit has a biased main clock signal generating means, and the phase of the output of the main clock signal generating means is completely compared with the phase of the output of each of the clock signal extracting means to achieve phase synchronization. A clock signal selection device comprising phase synchronization detection means for detecting all states, and selection means for selecting an output of the clock signal extraction means to be supplied to the main clock signal generation means based on the output of the phase synchronization detection means. method.