JPS6063800A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain high reliability without requiring the program of an address due to fuse melting, and to enable to salvage a defective memory cell as a satisfactory product without requiring special test equipment even if the defective memory cell is generated. CONSTITUTION:A conventional spare memory cell array and a spare decoder are removed, and data comparison circuits 41-0...41-7 and defective address storage detection circuits 42-0...42-7 are installed. When the defective memory cell is detected by the comparison circuit 41-0, the address corresponding to the defective memory cell at the time of writing is stored in advance by the above-mentioned defective address storage detection circuit. Selection of the defective memory cell at the time of writing is detected by comparing an input address and a storage address. When agreement of both is detected, right data are inputted to output buffers 23-0...23-7 by reverse rotation of the reading data from respective memory cell arrays 11-0...11-7 by sense amplifiers 22'-0...22'-7. As a result, selective melting of a fuse is not needed and reliability is improved. In addition, no special test equipment is needed, since detection of the defective memory cell and the inversion of the data are executed at the internal circuit of memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory in which data can be written and read, and particularly relates to a semiconductor memory in which data can be repaired in the case of a defective memory cell.

[Technical background of the invention]

BACKGROUND OF THE INVENTION With advances in microfabrication technology for integrated circuits, the storage capacity of semiconductor memories is increasing. As the number of memory cells configured within a memory of the same chip size increases, the probability of memory cell failure occurring within the memory chip also increases. In a semiconductor memory device, if even one defective memory cell occurs, the memory chip is considered defective and will be destroyed. Therefore, the larger the memory capacity, the more items are discarded as defective.

Conventionally, as a technique for saving a memory in which such a defective memory cell has occurred as a non-defective product, there is a known technique in which a spare memory cell array is prepared as shown in FIG.

In other words, is the first diagram the structure of a conventional half-body memory? It is a Zoronok diagram shown. This memory is an 8-bit parallel processing type that accesses 8 bits of data in parallel at a time, and has a plurality of memory cells each capable of writing and reading data! Eight memory cell arrays 1-0 to 11-7 having il- are Q-shaped. The memory cells in each of these memory cell arrays 11-O to I1-7 are assigned to one of the plurality of rows 13 according to the output of the row decoder 12 to which the addresses AO・Ao・′”−Aj・Aj are input. On the other hand, one of the plurality of column selectors 15 is selected by the output of the column decoder 14 to which the address a.+la6+...ai.shoulder is input. The book is driven.

Accordingly, each of the memory cell arrays 11-0 to 11-1
One column line return transformer 17 is driven for each of the column selection circuits 16-0 to 16-71/J provided corresponding to 1-7. When one column selection transnoster 17 is driven, one of the memory cells for each row selected in advance in the memory sensor arrays 11-10 to 11-7 is selected from the column of one valley. Hi 18
Each data input/output point 1910 to 19-
Connected to 7. That is, one memory cell in each memory cell array 1110 to 11-7 is selected by this, and after selection, data is convoluted and read from each memory cell. First, in the case of ÷overnight convolution, data input/output terminals 20-O to 20-7
Input data D supplied to. to D7 are applied to the data input/output points 19-O to 19-7 via input buffers 72J-0 to 21-7, respectively. In the case of data reading, the potentials of the upper and lower data output points 19-0 to 19-7 change depending on the data stored in the selected memory cell. This potential is detected as data by each sense amplifier 22-O to 22-7, and further this data is sent to the data input/output terminals 20-Off to 20-7 through each output/knofer 23-O to 23-7. Skin exposure data D. fx
It is outputted as stone D7. Note that each of the data input/output points 19-071i to 19-7 is provided with load circuits 24-O to 24-7, each consisting of a transnostar or the like.

Furthermore, in this semiconductor memory, each memory sensor array 1
When there is a defective memory cell in 1-O to 1-7, the spare memory cell arrays 251 to 25-7 are used to replace the defective memory cell in one row of memory cells. Memory cell array 1l 10 to 1
1-7. Ko 11 et al. 1fti
The memory sensor arrays 25-0 to 25-7 have the same address A as the address input to the previous row decoder 12. rA. +...Aj. 1fK is expected to be input
The decoder 26 of the memory cell array 1 is configured to select from memory cell arrays 1-10 to 11-7.
2 has itilJ's signal sword λ and Jmu.

First, my spare decoder 26v, as shown in Figure 2,
A decoder (MOS) for ringing, in which the address is manually input to the runners 3 and 9, consists of a transistor 32 and a heater 33 made of, for example, polysilicon, for address programming. at least 1
It has one.

Then, by selectively blowing out the upper pyfuse 33 by irradiation with a laser source, etc., the defective memory cells occurring in the memory cell arrays 11-0 to 11-7 can be dealt with.
7 addresses are preprogrammed. When the address corresponding to the defective memory cell in the housing is inputted, the spare decoder 26 is established, and 33 of the memory cell arrays 25-0 to 25-7 of 1+iti are selected by the output. At this time, the row decoder 12 is disabled by the signal from the spare decoder 26, and the memory cells in the memory cell arrays J7-072 to J11-7 are not selected.

In this way, the memory cell arrays 251-2 of the previous example
In the conventional memory provided with memory cell arrays 25-0 to 25-7, when a defective memory cell occurs in the normal memory cell arrays 11-1 to 1-7, it is stored in memory cell arrays 25-O to 25-7 of By replacing it with , a defective product can be made into a good product. Therefore, the yield of non-defective products can be increased, and the manufacturing cost can be reduced.

[Problems with background technology]

In the conventional semiconductor memory shown in FIG. 1, programming is performed by selectively blowing off the fuse 33 in the decoder 26 of the first address corresponding to the defective memory cell. This fusing is caused by laser light like the one mentioned above! This is done using the joules 2 and ＼ generated at this time when zero rays and excessive rays are flowed. In this way, in the past, it was necessary to blow out the fuse 33, and the bath: +norVc
A drawback is that when failure or melting occurs, a portion of the polysilicon scatters onto the surface of the chip, resulting in a decrease in reliability. In addition, Grodaram with an address like the above 6th one is >11 always rryet in the guiso dest process.

For this reason, the time required for this process is longer for each gram, resulting in an increase in price. In addition, since addresses are programmed using a special programmer, it is necessary for the user and the user to remedy the problem that occurs after the product is shipped. This is not practical as it requires a commercially available programmer.

[Purpose of the present invention] This invention was made by exploiting the above-mentioned features, and its purpose is to improve reliability by eliminating the need to program addresses by blowing fuses. a
The purpose of the present invention is to provide a semi-integrated memory that can be salvaged as a good product even if a defective memory cell fails without requiring a special tester.

[Summary of the invention]

In order to achieve the above purpose, in the present invention, when writing data at t1, data is read from the memory cell, and the data read out from the memory cell matches the written data. A comparison is made and both data match 'f!
:． If so, it is determined that this memory cell is defective, the address corresponding to the defective memory cell is stored, and the data 't++2+a+. 4. Data from memory cell to F.
When the iI'C address is matched with the address corresponding to the defective memory cell, fit (inverted data of the output data) is output from that memory cell.

[Embodiments of the invention]

Please refer to the diagram below to see if this is the right time for you! FIG. 3, part 0, for explaining ifi+4 is a block diagram showing the configuration of an embodiment of a semi-V7 body memory according to the present invention. This memory is of +08 bit parallel processing type, similar to the conventional one shown in FIG. 11-0 or 11-
Reference numeral 7 is a memory cell array having a plurality of memory cells each capable of writing and reading data in a conventional manner; 2 is a row decoder; 13 is a row decoder;
4t is a column decoder, 15 is a column selection yJ, l6-o to 16-7 are internal columns;
cRi3 (not shown in the figure) is provided with a column selection circuit, 1
8 is the column section, 9-0 to 19-7 are the data person output points,
20-0 to 20-7 are data D. or D7 input/output terminals, 21-0 or 2 No. 7 is input capanofer, 22
'-0 to 22'-ylrJ: Sense Ang, 23-
0 to 23-7 are output buffers, 24-0 to 24
-7 is a load circuit. In this embodiment 1 clear circuit, the spare memory cell array 2 provided in the conventional circuit is
5-0 to 25-7 and the spare decoder 26 are removed, and data comparison circuits 41-O to 4-7 are newly installed.
and invalid address storage detection circuits 42-0 to 42-2 are provided.

Each of the data ratio conversion circuits 4-10 to 41-7 is connected to each input buffer 21-0 to 21-2 when data is loaded into each memory cell array 11-0-11 to 1-7.
Output signal data from No. 7, writing dust of the above data, reading dust from the memory cell of l''J-address and data detected by each sense antenna 22'-0 to 22'-7. Detecting circuits 42-o to 42-7 for each of the above-mentioned address records 1 and 42-o to 42-7.
Address A is input to the ite decoder 12 and the column decoder l4. ,]τ,...Aj+Aj*
86*&6+"'ai*Ai is input, and both data match in each of the blocks Ichiyuhimaki circuit 4-10 to 41-7, and the address corresponding to the cold memory cell is entered. Complete list,
VC is becoming a problem.

Furthermore, top memory cell array 11-Oi 11-
After storing the data at 7V, each of the above-mentioned defective addresses L' 1, E detection times VJ42-t) to 42-7 compares the previously recorded address with the input address 4zL,...
Both addresses match (each sense an f22
A control signal is output from '-0 to 22'-7. Each sense an f22'-0. 'x-22'-7 outputs the inverted data of the detected data to each output buffer 23-θ to 23-7 when the above control number 48 is input from the defective address storage circuit kzi42-0 to 42-7. It is supposed to be done.

That is, in the above embodiment circuit, when data is stored in the memory cells in memory cell arrays 1-10 to 1-7, if the memory cells are normal, the t-in data and the read data match. This is what is being used. That is, each data comparison circuit 41-o to 41
If a data mismatch is detected at -7, it means that the memory cell is defective, and in order to use this defective memory cell as a good product, it is only necessary to use the inverted data of the lying data. Become. Therefore, when writing data, the address corresponding to this defective memory cell is stored in advance in the address memory detection circuits 42-O to 42-7, and when the data record C is output after data writing 1, this defective memory cell is The selection is determined by comparing the input address and the memory address, and when a match between the two addresses is detected, the sense amplifiers 22'-0 to 22
At '-7, all of the IILC output data from each of the memory cell arrays 11-0 to 1-7 is inverted so that the correct data is input to the output buffers 23-0 to 23-7K.

In this manner, in the above-described disaster example circuit, addresses corresponding to defective memory cells are stored in advance, and when data is read after data recording, all input addresses are compared with the above-mentioned storage addresses, and the defective memory cell is selected. When both addresses match, the inverted data of the read data from this defective memory cell is output as data.
The conventional four-choice fusing of the heater is unnecessary.In other words, in the example circuit, in order to output normal data, data comparison, address storage, address comparison, Since only the signal processing of data inversion is performed, reliability can be significantly improved compared to conventional methods.Furthermore, detection of defective memory cells and data inversion are performed in the internal circuit of the semiconductor memory. Therefore, it is possible to salvage a defective product as a good product without using any special test-like equipment. FIG. 4 shows the configuration of a semi-dedicated memory according to another embodiment of the present invention. 2 is a block diagram. In the embodiment circuit of FIG. 2, defective address storage detection circuits 42-0 to 42-7 are provided independently for each bit, but in this embodiment circuit, one circuit for 8 bits is provided. In other words, according to the comparison results of each data comparison circuit 4-10 to 4-7, the defective address storage detection circuit 43 is installed in parallel. The address corresponding to the memory cell is stored in advance.Then, when reading data after the data V1 has passed, the storage address and the input address are compared, and if the two addresses match, the bit where the invalid memory cell exists is sensed. A control signal (g) is output to the amplifier 22' to cause the inverted data read from the memory cell to be output.

v. FIG. 5 is a prosock diagram showing the implementation of a half-body memory according to still another embodiment of the present invention.

In the circuit of the embodiment shown in FIG.
The No. 1B manual power route from No. 7 and the Hakugo output route from Sensuanzo 22'-0 to 22'-7 are independent. However, signals are not transmitted and delayed simultaneously on both of these paths, and the signal transmission periods are not equal. Therefore, in this embodiment circuit, data comparison circuits 41'-0 to 41'-7 whose output state can be set to high impedance are provided, and the defective address storage detection circuit 43 and the sense amplifier 22 are provided.
'10 to 22'-7 and data comparison circuit 41'-
The signal path between 0 and 41'-7 is also used.

The sixth example is a circuit diagram specifically showing the buffer 2, the sense amplifier 22', and the data comparison circuit 4 in the embodiment circuit of FIG. 3 for the 0th bit. The input cover 21-0 is input data D. k
Four φ-type inverters 51 to 54 are arranged so as to have a k-th inversion center, and the two inverters 54, 5 .
Two MOS} runnostars 55, 56 each having the output of 7 as a dirt input, and the memory cell arrays 11-O to 11-7 are inserted between the output terminals of the two inverters 53, 54 and the ground point. The circuit is composed of two MOS transistors 57 and 58, into which a signal R, which is set to 0 level when data convolution is performed, is input to each dart. This person is 16' in Kabuffa 2 No. 10.
A MOS transistor 57 in which the number R is set to 0 level.
．． 58 are both turned off, resulting in the two M
OS} The transistors 55 and 56 are human data D. 10,000 is turned on and the other is turned off. Here is the human power data D. When D0 is at the 1 level, the MOS transistor 55 is turned on and the MOS transistor 56 is turned off, and when the input data D0 is at the O level, on the contrary, the MOS transistor 55 is turned off and the MOS transistor 56 is turned off. MOS} Runnostar 56 is turned on, so human power data 1].

As it is, this person's level is 21-Of
The signal is supplied to the memory cell array via the memory cell array.

The sense amplifier 22'-0 uses the potential of the data read from the memory cell array as a reference voltage from the MOS transistors 61 to 65. The output from the voltage comparison circuit 66 is inputted, and the bladder output data from the memory cell array is inputted. ,do as C
f: The latch circuit 71 with which this latch circuit W? 571
+'Retained data d. , do either 10,000 t
itlJ look up B4jiN. ．． Two MOS transistors 7 for switches and switches that output to the outputs P and F according to No.
2.73.

The data comparison circuit 4I-0 is the FJ'lJ reporter data D.
An inverter 8 which inverts the output of the inverter 52 which is set to the same level as the signal H; At the timing of the good signal R' when σ is slightly σ, the output of the ratio circuit 87 is fully powered and the signal SL is generated. and this signal L. Fully reversed - UL. It is composed of an inperter 92 that forms a t-shape.

In this circuit of FIG. 6, when data is written to the memory cell array, input data D is input. level is set to 10,000 levels. For example, if this data is set to 1 level, the signal R is set to 0 level during data writing, so the output stage MOS in the input buffer 21-θ
The transistor 55 is turned on and the transistor 56 is turned off, and 1 level is supplied to the memory cell array as write data. After writing the data, the input data D0 is set to its original level, and the signal R is set to the 1 level. Signal R
When set to 1 level, the MOS transistors 57 and 58 of the input buffer 21-OP:3 are turned on, which turns both the BIOS transistors 55 and 56 off, and the output of the input buffer 21-0 is turned on. is placed in a high impedance state. Thereafter, data is transferred from the same memory cell to which the data was written to iilr. The signal is output from the sense amplifier 2 and supplied to I-o. However, if the memory cell into which the data is stored is defective, the data supplied to the sense amplifier 2/-0 will be level 0. Then, the 0 level is latched as the data do, and the 1 level is latched as the data do in the A, , and CH circuits 7 in the sense amplifier f22'-θ. Therefore, data comparison circuit 4
y of the MOS transistor 85 of the comparator circuit 87 within no-θ
- The gate input of the MOS transistor 86 is set to the 1 level, and the gate input of the MOS transistor 86 is set to the 0 level. On the other hand, input data 1)o is set to level 1 in advance, so
1.Comparison circuit 870MOS} The gate input of the MOS trannostar 83 is set to 0 level, and the dart input of the MOS trannostar 84 is set to 1 level K. At this time, the comparison circuit 8
The output of 7 becomes 1 level, and after that, the 1st key number 1 bit is set to 1 level, and the signal becomes L. is 0 level,
Double number L. are each set at one level. That is,
If the memory cell is defective and the saved data and 01 output data do not match, the signal is L. is set to level 0, and the signal port is set to level 1. Conversely, if the memory cell is normal, signal Lo is set to level 1, and signal 4 is set to level 0, respectively.

FIG. 7 shows a signal L provided in the defective address storage detection circuit 42-θ. , Lo is a circuit diagram showing a {11゛ζ configuration of a latch circuit. This latch circuit 100 is composed of MOS} runnostars 101 to 106, and 11 consisting of two resistors 107, 108, a capacitor 109, and an impark 110. A power-on reset circuit generates a pulse signal for a predetermined period of time when the power is turned on. Signal generation circuit 11
By the output of , one output B is reset in advance to 0 level and the other output Po is reset to 1 level.

Then, when the output "0" of the data comparison circuit 41-0 is set to the 1 level, the MOS transistor 106 is turned on, so the signals Po and Po are set to the level R opposite to the reset state, and the Lo When is set to level 0, the MOS} runnoster 106 is turned off, so the signal P.,6 is held at the level of the reset state.1' That is, in the latch circuit 100 of FIG. , 4. If a good memory cell exists, one output PO is set to 0 level, and the other output B is set to 1 level.

FIG. 8 shows the defective address; memory detection circuit 42"-0
2 is a circuit diagram showing the configuration of a defective address storage circuit 120 provided therein and storing addresses corresponding to defective memory cells. FIG. This circuit 120 has an input address Ao...
・Aj, aQ...a. are respectively input and the output P of the latch circuit 100 shown in FIG. A plurality of MOS transistors 12 controlled by switches and switches, each of these MOS transistors connected to the other end of the transistor 121, and inverters 122 and 123 each having a value of 2 and ρ connected in series with each other, and each of the above two The output protrusion of the latch circuit 100 shown in FIG.
11 with multiple MOSL transistors 124 controlled by
4 has been completed.

In this circuit, when the latch circuit 100 is reset, the signal P. by MOS transistor 2
J is turned on, and each MOS} runnostar 124 is turned off due to the signal error, so that each inverter 23 outputs the input address Ao-Ajrao~a as it is, and each inverter 24 outputs its inverted address. Address A. -A, +116~a1 is output as J. Here, when a mismatch between the write data and the exposed data is detected by the data comparison circuit 4NO-O, the output Po+Po of the latch circuit 100 causes each MOS
}The lamp disk 121 is turned off, and each MOS}lannostano 24 is turned on. The input address at this time corresponds to the defective memory cell, and this address is the address A' in a closed loop consisting of inverters 22, 123 and MOS transistor 24. rA'6+"・
κjlrj'ra/ola/, T"'"i+r.

Figure 9(u). (b) is provided in the defective address register 1 and code detection circuit 42-0, and compares the memory address of the defective address storage circuit 120 shown in FIG. 8 with the input address, and uses the result of this comparison. Accordingly, the two MOS transistors 72.7 in the sense amplifier 7°22'
↑}+11 control signal No, N for controlling 3
, is a circuit diagram showing the configuration of a defective address detection circuit that generates . This circuit includes bit address comparison circuits 130 shown in FIG. 9(a) for the number of bits of the address. This circuit 130 includes a load MOS trannostar 131,
It is composed of four drive MOS} runnostars 132 to 135, and has an input voltage of 1, 1, 2, 1, 2, 3, 3, 4,
) or ay+8, (y-0 to i) and the storage address A'YA of the defective address storage circuit 120 shown in FIG.
When 1 or a'+&' match, an Orepenore signal yyE or F is output. The outputs EX, Fy from the address XY comparison 1 same path 130 are
0 is input to the NOR circuit 141 in the 91st step (b). This NOR circuit 14 outputs the output E from the circuit 130 of FIG. 9(a) when the signal PO is set to 0 level.
When F is all 0 level, xy, that is, a defective memory cell exists, and when the input address matches the address corresponding to the defective memory cell, its output is set to 1 level. Also, this signal No. is set to N by the inpertano 42. is reversed.

As described above, the output No from this defective address detection circuit becomes 1 level and 0 only when Po is at O level and the input address matches the memory address in the defective address storage circuit 120 shown in FIG. are set for each level. At this time, the signals No, N,
As a result, the MOS transistor 72 of the MOS transistors 72 and 73 in the sense amplifier 7'22-o is turned on, and as a result, the data 6 having the opposite level to the data read from the memory cell is sent to the output buffer. supplied to

FIG. 10 shows a circuit configuration of the defective address storage detection circuit 43 provided in the embodiment circuit of FIG. 4, corresponding to the circuit shown in FIG. 9(b). In this defective address storage detection circuit 43, a signal L latch circuit 100 as shown in FIG. 7 of the iIT record, a defective address storage circuit 120 as shown in FIG. A bit address comparison circuit 130 as shown in Figure (a) is provided. The output from each latch circuit 100 and the output from the bit address comparison circuit 130 Ex. F is input to each NOR circuit 151, and the output of each NOR circuit 15 is a signal, and these signals are input to each inverter 52.
is inverted from No to N7.

FIG. 11 also shows the configuration of a circuit corresponding to the circuit of FIG. 10 which is suitable for the defective address storage detection circuit 43 in the circuit of the embodiment shown in FIG.

In this circuit, the output Pa to -1"- of the circuit shown in FIG.
, is input to the Not71 (!l path 161) to form the signal Q, which is inverted by the input signal 162 to form the signal δ. Here, it is determined that there is a defective memory cell. SobaP.

Any one of P7 to P7 is set to 1 level, and thereby Q is set to O level and σ is set to 1 level. The signal Q is the output Ex from the bit address comparison circuit 130.
It is input to another NOR circuit 163 together with +Fy.

The output of this NOR circuit 163 is set to 1 level only when a defective memory cell exists and the storage address and input address match.

The output of the NOR circuit 163 is inputted in parallel to a NAND circuit 164 in which each of the signals P7 to NOR is inputted in parallel. These NAND circuits 164 detect in which bit a defective memory cell exists, and the sense amplifier 2! This is used to form signals No. to N7 for switching control of the MOS transistors 73 within the MOS transistors. For example, if the address corresponding to the defective memory cell that is input to the NOR circuit 163 is the 0th bit, then only the NO is set to the 0th bit. The remaining N to N7 are set to 1 level. Furthermore, each signal N
O to N7 are inverted fan to four by each of the plurality of inverters 165. The output L signal from the in-theta circuit 165 is used to control the MOS transistor 72 in the sense amplifier 2.

Here, the above signal N. When JL is set to 0 level, signal starvation is set to 1 level. In this case, the MOS transistor 72 is turned on in the sense amplifier 2 no. 10 of the 0th bit, and a data block having a level opposite to that of the data read from the memory cell is supplied to the output buffer, and the remaining sense amplifier 02z' -1 to 2 to -7, the MOS} runnoster 73 is turned on, and data d1 to d7 at the same level as the data read from the memory cell is supplied to each output buffer. Note that the signals Q, formed by this circuit,
Q may be supplied to the circuit shown in FIG. 8 instead of {i3p,p used in the defective address storage circuit 120 shown in FIG. 8.

FIG. 12 shows the configuration of an output circuit for signals L, T, and 100 suitable for the data comparison circuit 41' provided in the embodiment circuit of FIG. In this case, ■ is input instead of the letter L in FIG. In this circuit, the comparison circuit 87 in FIG.
Two vD3Js are installed to sequentially invert the output of
l inverters 171 and 172, and a power supply voltage V. Two MOSs are inserted in series between the application point and the ground point and use the outputs of the two inverters 171 and 172 as inputs.
}The transistors 173 and 174 are also inserted between the VC application point and the ground point, and the inverters 172 and 171
Two MOS transistors 175, 176 whose outputs are input as inputs, and these MOS transistors 175, 1
76 connection point and the ground point, respectively, to the dart signals R',! is input MOS} transistor 17
9, 180, a MOS transistor 177 which is inserted between the output end of the inverter 171 and the ground point and receives an inverted signal π of the signal π as f-to input;
- Inserted between the output end of 172 and the ground point, and
MOS with No. 8 Ie as date input} Lannostar 178
It is composed of.

In this circuit, after the signal is output from the comparison circuit 87, the positive signal is set to 0 level, and the MOS transistor 177
, 178, and 180 are both turned off. In addition, the signal k is changed to ゜゛1'' level R, and the MOS} Runnostar 179
1': ], turns on, and the fan and itself are connected. At this time,
Depending on the output from the comparator circuit 87, one of the two MOS transistors 173 and 174, 175 and 176 is turned on and the other one is turned off, and the levels of the signals L, -[, ■ are set. . On the other hand, from the defective address storage detection circuit 43, the sense address 22'10 to 2! -7
When supplying a signal to , the signal W is set to 1 level and the MOS transistors 177, 178, and 180 are turned on. Then, MOS transistors 173 to 17
6179 are all turned off. , the self is placed in a high impedance state. At this time, the low signal P, which is set to the '0'' level, is stably latched.

FIG. 13 shows an alternative example of the comparator circuit 87 shown in FIG. 6. In this circuit, the input from input buffer 2 is once latched by latch circuit 18 and then input to comparator circuit 87, and the output from this circuit is latched by another latch circuit 182. be.

Note) Both latch circuits 181 and 182 are controlled by the signal W.
You can do it by.

FIG. 14 shows another example of the sense amplifier f2z'. In the device shown in FIG. 6, data d and d having opposite levels are formed in response to the bladder release data from the memory cell, and one of these is set to Hill. No. 1 N,
By selectively turning on the MOS} lannostars 72 and 73 according to the output voltage, υ is output. However, in the one shown in FIG. 14, an inverter 19 and two h4OS transistors 192 and 193 are used,
Control {Based on R numbers N and NK, readout button d is
The signal is inverted by an inverter 191 and output.

Note that this invention is not limited to the above-mentioned actual foil example, and various modifications are possible. For example, in the above example, td1
Although only one bit of memory cells can be processed, it is also possible to provide a plurality of defective address increase circuits and perform processing for iy number of defective memory cells. In the above embodiment, a 2A case was explained in which each memory cell array 11 uses a RAM cell in which data can be written and read. : The present invention can also be applied to an EPROM memory using a MOS transistor having an MNOS structure as a memory cell. +1 writing of data in EPROM is done using a special Zorogramma, and when writing this data, the same i? 1? ．． A comparison is made with the output data, and if a defective memory cell is found, its address may be stored in the memory cell itself as part of the data.

[Da'b of invention]

As explained above, according to the present invention, reliability can be increased by eliminating the need for 70 programs of addresses due to fuse blowout (c), and moreover, it is possible to improve reliability in cases where defective memory cells occur. It is possible to provide a semiconductor memory that can be salvaged as a non-defective product by internal operation without using a test stage.

[Brief explanation of the drawing]

Figure 41 is a block diagram showing the configuration of a conventional semiconductor memory.
Fig. 2 is a circuit diagram showing the structure of a spare decoder of the memory shown in Fig. 1, and Fig. 3 is a circuit diagram showing an implementation of the present invention {/11It (Process 1Δ, 41'!7 showing the structure of such a semiconductor memory).
” and No. 5141 respectively indicate structures of semiconductor memories according to other embodiments of the present invention. s
6 to 14 are a circuit diagram specifically showing a part of the circuit of each of the embodiments described above, and a circuit diagram showing an example of its house shape, respectively. 11...Memory cell array 13...7] Pukobe 13
...line i%i! , 14...column decoder, 15...
Column No. 1, 16... Column selection circuit, 18... Column A, C 21... Human buffer, 22... - Hinsuanfu 0
, 23...I1i non-puffer, 4th...Dake ratio circuit, 42.43...Failure address record 1, ζ detection circuit, 66...'iH, phase ratio 11/other circuit, 7th... -Latch circuit, 87...Ratio ζ-no circuit, 100...Latsua circuit, 120...Defective address. j self 1,4 circuit,
130...Bit address comparison circuit. -616- -617- -618-

Claims (5)

[Claims] (1) Writing data selected by address input,
A memory cell array having memory cells to be read, data written to the memory cells, and data 1. Detection means for detecting a defective memory cell by performing a match comparison of data detected from memory cells at the same address after loading, and a defective address corresponding to the defective memory cell detected in the above ten stages storage means, and data bc output from this memory cell on one day when the address input when reading data from the memory cell after data storage matches the address stored in the defective address storage means. and an inverted data output means for outputting inverted data. (2) a plurality of the memory cell arrays are provided;
2. The semiconductor memory according to claim 1, wherein said defective address storage means is provided independently for each memory cell array. (3) If a plurality of the memory cell arrays are provided,
, n'lJ defective address storage means is provided in common for each memory cell array.
Semiconductor memory described in section. (4) The inverted data output means includes comparison means for performing a match comparison between the stored address in the defective address storage means and the manual address; 2. The semiconductor memory according to claim 1, further comprising a selection means for selectively outputting any one of the data and its inverted data. (5) The data output means outputs the data from the memory cell according to the ratio between the comparison means and the comparison means that compares the storage address in the defective storage means with the input address. <B: Semiconductor memory recited in column n1 and item 41 of the patent application consisting of means for inverting and outputting data.