JPS6052656U - 回路基板 - Google Patents
回路基板Info
- Publication number
- JPS6052656U JPS6052656U JP1983145618U JP14561883U JPS6052656U JP S6052656 U JPS6052656 U JP S6052656U JP 1983145618 U JP1983145618 U JP 1983145618U JP 14561883 U JP14561883 U JP 14561883U JP S6052656 U JPS6052656 U JP S6052656U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- substrate
- semiconductor
- covering
- abstract
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第1図は従来の回路基板の斜視図、第2図は本考案実施
例の基板の平面図aと断面図すである。 1・・・基板、2・・・半導体、3・・・被覆体、4,
4・・・透孔。
例の基板の平面図aと断面図すである。 1・・・基板、2・・・半導体、3・・・被覆体、4,
4・・・透孔。
Claims (1)
- 基板と、基板上に載置された半導体と、半導体を覆い基
板上に設けられた被覆体と、被覆体の少なくとも一部に
添って基板に設けられた透孔とを具備した事を特徴とす
る回路基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983145618U JPS6052656U (ja) | 1983-09-19 | 1983-09-19 | 回路基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983145618U JPS6052656U (ja) | 1983-09-19 | 1983-09-19 | 回路基板 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6052656U true JPS6052656U (ja) | 1985-04-13 |
Family
ID=30324378
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1983145618U Pending JPS6052656U (ja) | 1983-09-19 | 1983-09-19 | 回路基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6052656U (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012158228A (ja) * | 2011-01-31 | 2012-08-23 | Advics Co Ltd | ソレノイド制御装置 |
JP2017054990A (ja) * | 2015-09-10 | 2017-03-16 | パナソニックIpマネジメント株式会社 | 発光装置 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5012249B1 (ja) * | 1969-03-31 | 1975-05-10 |
-
1983
- 1983-09-19 JP JP1983145618U patent/JPS6052656U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5012249B1 (ja) * | 1969-03-31 | 1975-05-10 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012158228A (ja) * | 2011-01-31 | 2012-08-23 | Advics Co Ltd | ソレノイド制御装置 |
JP2017054990A (ja) * | 2015-09-10 | 2017-03-16 | パナソニックIpマネジメント株式会社 | 発光装置 |
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