JPS6049637A - Mounting method of semiconductor substrate - Google Patents
Mounting method of semiconductor substrateInfo
- Publication number
- JPS6049637A JPS6049637A JP58157344A JP15734483A JPS6049637A JP S6049637 A JPS6049637 A JP S6049637A JP 58157344 A JP58157344 A JP 58157344A JP 15734483 A JP15734483 A JP 15734483A JP S6049637 A JPS6049637 A JP S6049637A
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- temperature
- semiconductor substrate
- case
- heated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29144—Gold [Au] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83048—Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
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- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体基板のマウント（固着）の高品質化を
目的としており、特に急激な温度変化に弱い半導体素子
で形成された半導体基板のマウント方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention aims to improve the quality of mounting (fixing) semiconductor substrates, and particularly relates to a method for mounting semiconductor substrates formed of semiconductor elements that are susceptible to rapid temperature changes.
最近の半導体素子は、高集積化や高速性能化のため、一
般と、素子形状の微細化や接合のシャロー化が進められ
ている。In order to achieve higher integration and higher speed performance, recent semiconductor devices are generally becoming smaller in element shape and shallower in junction.
ところが、この様な半導体素子は、急激な温度変化を受
けると、素子構造に変化が起き易く、特性不良を生じる
場合が、多くなってきている。However, when such a semiconductor element is subjected to a sudden temperature change, the element structure tends to change, and characteristics are increasingly being caused.
実際、その現象は、組立のマウント時に多く発生し、組
立不良の多発をまねいている。一般に、半導体基板のマ
ウントは、半導体基板を、軟質ハンダや、共晶合金によ
る硬質ハンダ及び導電性レジンペースト等を用いて、マ
ウント部（基イに支持台）表面に接着することによって
行なわれているが、現在、主として、使用されているの
は、硬質ハンプである。この従来型のマウント方法例よ
れば、半導体基板は室温に保存された状態から、４００
℃前後に加熱されたマウント部表面にいきなシ、圧接さ
れるために、急峻な温度変化を受ける。In fact, this phenomenon often occurs during mounting during assembly, leading to frequent assembly defects. Generally, semiconductor substrates are mounted by adhering the semiconductor substrate to the surface of the mount (base and support) using soft solder, hard solder made of eutectic alloy, conductive resin paste, etc. However, currently, rigid humps are mainly used. According to this example of a conventional mounting method, a semiconductor substrate can be stored at room temperature for 400 minutes.
Because it is pressed into contact with the surface of the mount, which is heated to around ℃, it is subject to steep temperature changes.
従って、従来性なわれてきた、この様なマウント方法は
、高性能ＩＣの特性劣化をもたらし、組立良品率を低下
させる原因となるという欠点があった。Therefore, this mounting method, which has been conventionally used, has the disadvantage of causing deterioration of the characteristics of high-performance ICs and lowering the assembly rate of non-defective products.
そこで、本発明の目的は、急加熱に弱い半導体素子の、
特性を殆んど変動せずに、マウントできる様な新しいマ
ウント方法を提供することにある。Therefore, an object of the present invention is to reduce the temperature of semiconductor elements that are susceptible to rapid heating.
The object is to provide a new mounting method that allows mounting with almost no change in characteristics.
つまり、本発明では、常温に保存された半導体基板を、
室温と溶融温度の中間の温度にゆっくシと加熱して、そ
の後、合金化用金属を乗せ、かつ、高温に加熱されたマ
ウント部表面に圧接することを特徴とするマウント方法
を提供する。この方法によれば半導体基板は、従来方法
の様な急峻な温度変化を受けることはなくなり、緩和さ
れたものになる。従って、半導体素子の特性劣化は、な
くなシ、組立良品率もきわめて、高いものを期待できる
。In other words, in the present invention, a semiconductor substrate stored at room temperature is
To provide a mounting method characterized by slowly heating to a temperature intermediate between room temperature and melting temperature, then placing an alloying metal and press-welding it to the surface of a mount part heated to a high temperature. According to this method, the semiconductor substrate is not subjected to steep temperature changes unlike the conventional method, and the temperature changes are relaxed. Therefore, it is possible to expect that there will be no deterioration in the characteristics of the semiconductor element, and that the assembly yield will be extremely high.
本発明の第１の実施例を第１図（ａ）〜（Ｃ）に基づい
て説明する。A first embodiment of the present invention will be described based on FIGS. 1(a) to (C).
ダイシングされた６ｘｘ角の半導体チップ６をセラミッ
ク・ケース１のマウント部２に、マウントする場合につ
いて説明する。A case will be described in which a diced 6xx square semiconductor chip 6 is mounted on the mount portion 2 of the ceramic case 1.
まず、上記ケース１のマウント部２に硬質ハンダ材Ａｕ
−８ｉ３を乗せ、共晶合金温度より高めの４５０℃に、
マウント用の加熱装置（マウンター）４で加熱しておく
。（第１図（ａ））
次に、上記チップ６を本発明によるところの中間の温度
２４０℃に保った予備加熱用のポット・プレート７上に
３０秒間乗せて、その温度まで、ゆっくシと加熱する。First, a hard solder material Au is attached to the mount part 2 of the case 1.
-8i3 is placed at 450℃, which is higher than the eutectic alloy temperature.
It is heated with a heating device (mounter) 4 for mounting. (FIG. 1(a)) Next, the chip 6 is placed on a preheating pot plate 7 maintained at an intermediate temperature of 240° C. for 30 seconds, and slowly heated to that temperature. and heat.
（第１図（ｂ））その後、上記チップ６の温度を２４０
’Ｃ付近に保持したままで、ケース１のマウント部２
に水平に圧接させ、同時に数回擦シ動かして（スクラビ
ング）マウントを行なう。（第１図（Ｃ））本発明のマ
ウント方法を使用した上１己テッグ６は、特性劣化が全
く見られず、又、組立良品率も、従来法に比べ格段に向
上している。(Fig. 1(b)) After that, the temperature of the chip 6 was increased to 240°C.
While holding it near 'C', mount part 2 of case 1.
Mount by applying pressure horizontally to the surface and scrubbing several times at the same time. (FIG. 1(C)) In the case of the upper one-piece TEG 6 using the mounting method of the present invention, no deterioration in characteristics was observed at all, and the assembly rate was also significantly improved compared to the conventional method.
即ち、本発明のマウント方法によれば、温度変化が従来
の方法よシ、緩和され、その分チップに与えるダメージ
も小さくなシ、特性劣化や特性不良の発生は激減する。That is, according to the mounting method of the present invention, temperature changes are more relaxed than in the conventional method, damage to the chip is correspondingly reduced, and the occurrence of characteristic deterioration and characteristic defects is drastically reduced.
尚、上記実施例に於いて、温度変化をもっと緩かなもの
にする為には、熱容量の大きいセラミック基板上に、チ
ップを配列して、中間の温度を４５０℃に設定したホッ
ト・プレート上に、乗せてゆっくりと加熱すれば良い。In the above example, in order to make the temperature change more gradual, the chips were arranged on a ceramic substrate with a large heat capacity and placed on a hot plate with the intermediate temperature set at 450°C. , just put it on top and heat it slowly.
この方法だと、（に良好なマウントが可能となる。This method allows for good mounting.
第２の実施例を第２図に基づいて説明する。第１の実施
例と同様な半導体チップ９をケース１゜のマウント部表
面１１にマウントする場合について説明する。A second embodiment will be described based on FIG. 2. A case will be described in which a semiconductor chip 9 similar to that of the first embodiment is mounted on the mount surface 11 of the case 1°.
内部に数個のヒーター１４，１５．１６を有し、左側Ａ
から右側りに対して室温から、溶融温度４５０℃まで、
ゆるやかな温間勾配が付く様に制御されたケース加熱用
の装置ｄ１７の模式図を第２図に示す。まず、室温に保
れた半導体チップ９を室温に保れたケース１０のマウン
ト部１１に、は−５＝
＋ ｗ −ｂ Ａｕ −Ｍ ｉハンダ片１２を乗せた上
に置く。It has several heaters 14, 15, 16 inside, and the left side A
From room temperature to the right side, to a melting temperature of 450°C,
FIG. 2 shows a schematic diagram of a device d17 for heating the case, which is controlled to provide a gentle warm gradient. First, the semiconductor chip 9 kept at room temperature is placed on the mounting part 11 of the case 10 kept at room temperature, on which -5=+w-b Au-M i solder piece 12 is placed.
そして、それをケース加熱用の装置１７の左側Ａ１８に
置く。Then, it is placed on the left side A18 of the device 17 for heating the case.
次にケース１０を右側の８点１９（温度１４０℃）に移
動する。約１５秒後にケース１０を更に右側の０点２０
（温度２８０℃）に移動する。その場合、半導体チップ
９が、ケース１０のマウント部１１によく密着する様に
、コレット１３で押圧する事が必要である。更に、約１
５秒後に、ケース１０を右側の点Ｄ２１（温度４５０℃
）に移動する。そして、テップ９が充分に温まったら、
スクラビングを行ない、マウント部表面１１によく接着
させる。そして、ゆっくシと冷却する。Next, the case 10 is moved to the eight points 19 on the right side (temperature 140° C.). After about 15 seconds, move case 10 further to the right side, 0 point 20.
(temperature 280°C). In that case, it is necessary to press the semiconductor chip 9 with the collet 13 so that it comes into close contact with the mounting portion 11 of the case 10. Furthermore, about 1
After 5 seconds, move the case 10 to point D21 on the right side (temperature 450°C).
). Then, once Step 9 has warmed up enough,
Scrubbing is performed to ensure good adhesion to the mount surface 11. Then, cool it down slowly.
本発明のこの方法によれば、中間の温度は１４０℃と２
８０℃の２段階となり、更にケース自体の熱容量も加味
される為、チップに対する温度変化は、きわめて緩和さ
れたものになシ、マウント時に於ける特性劣化の問題は
なくなる。即ち、組立良品率が格段に向上すると共に、
高品質も保証されるという利点がある。According to this method of the invention, the intermediate temperatures are 140°C and 2°C.
Since there are two stages of 80° C. and the heat capacity of the case itself is also taken into account, temperature changes to the chip are extremely moderate, and there is no problem of characteristic deterioration during mounting. In other words, the assembly quality rate is significantly improved, and
It also has the advantage of guaranteeing high quality.
６−
以上、実施例について説明してきたが、本発明の主要部
分は、半導体チップをゆっくりと加熱してマウントする
事にあり、上記実施例に限定されるものではなく、特許
請求に示される全ての範囲に及ぶ。従って、本発明によ
れば、急加熱に弱い高性能ＩＣの特性を損なわないマウ
ントが可能となり、高品質化及び組立歩留向上に、絶大
な効果がある。6- Although the embodiments have been described above, the main part of the present invention is to slowly heat and mount the semiconductor chip, and is not limited to the above embodiments, but includes all the embodiments shown in the claims. Covers a range of. Therefore, according to the present invention, it is possible to mount a high-performance IC that is susceptible to sudden heating without impairing its characteristics, which has a tremendous effect on improving quality and assembly yield.
第１図（ａ）〜（Ｃ）は、第１の実施例を断面でみち模
式図で、第２図は、第２の実施例を断面でみた模式図を
示す。
尚、第１図計いて、１・・・・・−セラミック・ケース
、２・・・・・・ケースのマウント部、３・・・・・・
Ａｕ Ｓ ｔ ハｙダ片、４・・・・・・マウンター、
５・・・・−・ヒーターＡ、６・・・・・・半導体チッ
プ、７・・・・・・予備加熱用はホット・プレー、８・
・・・・・ヒーター、を示す。
第２図に於いて、９・・・−・半導体チップ、１０・・
・・・・セラミック・ケース、１１・・・・・・ケース
のマウント部、１２・・・・・・Ａｕ Ｓｔハンダ片、
１３・・・・・・コレット、１４・・・・・・ヒーター
Ｂ１１５・・・・・・ヒーターＣ１１６・−・・・・ヒ
ーターＤ１１７・・・・・−ケース加熱用の装置、１８
・・・・−・ケース加熱用の装置のＡ点、１９・・・・
・・ケース加熱用の装置のＢ点、２０・・・・・・ケー
ス加熱用の装置の０点、２１・・・・・・ケース加熱用
の装置のＤ点を示す。
リ ）1A to 1C are schematic cross-sectional views of the first embodiment, and FIG. 2 is a schematic cross-sectional view of the second embodiment. In addition, as shown in Figure 1, 1... - Ceramic case, 2... Case mount, 3...
Au S t Hyda piece, 4...Mounter,
5...- Heater A, 6... Semiconductor chip, 7... Hot play for preheating, 8...
...Indicates a heater. In FIG. 2, 9...--semiconductor chip, 10...
... Ceramic case, 11 ... Case mount part, 12 ... Au St solder piece,
13... Collet, 14... Heater B115... Heater C116... Heater D117... Case heating device, 18
...... Point A of the device for heating the case, 19...
. . . Point B of the device for heating the case, 20 . . . Point 0 of the device for heating the case, 21 . . . Point D of the device for heating the case. )
Claims (3)
に合金化用金属を介在させ、半導体基板を平行に圧接す
るマウント方法に於いて、該半導体基板を予め、予備加
熱することを特徴とする半導体基板の寸つント方法。(1) A mounting method in which an alloying metal is interposed on the surface of a mount portion heated to a temperature necessary for mounting, and a semiconductor substrate is pressed in parallel with the semiconductor substrate, which is characterized in that the semiconductor substrate is preheated in advance. How to dimension semiconductor substrates.
との間の、はぼ一定の温度となる様なものであることを
特徴とする特許請求範囲第（１）項記載の半導体基板の
マウント方法。(2) The semiconductor substrate according to claim (1), wherein the preheating is such that the temperature is approximately constant between room temperature and the temperature required for mounting. How to mount.
導体基板を徐々に加熱することを特徴とする特許請求範
囲第（１）項記載の半導体基板のマウント方法。(3) The method for mounting a semiconductor substrate according to claim (1), wherein the preheating step is to gradually heat the semiconductor substrate from room temperature to a predetermined temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58157344A JPS6049637A (en) | 1983-08-29 | 1983-08-29 | Mounting method of semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58157344A JPS6049637A (en) | 1983-08-29 | 1983-08-29 | Mounting method of semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6049637A true JPS6049637A (en) | 1985-03-18 |
Family
ID=15647628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58157344A Pending JPS6049637A (en) | 1983-08-29 | 1983-08-29 | Mounting method of semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6049637A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0226239U (en) * | 1988-08-08 | 1990-02-21 | ||
| JPH04111780U (en) * | 1991-03-14 | 1992-09-29 | 新電元工業株式会社 | electronic parts equipment |
| EP3163601A3 (en) * | 2009-01-23 | 2017-08-09 | Nichia Corporation | Method of producing a semiconductor device by bonding silver or silver oxide on a surface of a semiconductor element with silver oxide on a surface of a base |
| CN112967957A (en) * | 2021-02-07 | 2021-06-15 | 深圳市东飞凌科技有限公司 | Eutectic device and transistor packaging eutectic system |
-
1983
- 1983-08-29 JP JP58157344A patent/JPS6049637A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0226239U (en) * | 1988-08-08 | 1990-02-21 | ||
| JPH04111780U (en) * | 1991-03-14 | 1992-09-29 | 新電元工業株式会社 | electronic parts equipment |
| EP3163601A3 (en) * | 2009-01-23 | 2017-08-09 | Nichia Corporation | Method of producing a semiconductor device by bonding silver or silver oxide on a surface of a semiconductor element with silver oxide on a surface of a base |
| EP3163602A3 (en) * | 2009-01-23 | 2017-08-09 | Nichia Corporation | Method of producing a semiconductor device by bonding silver on a surface of a semiconductor element with silver on a surface of a base in air or in an oxygen environment |
| EP3151268A3 (en) * | 2009-01-23 | 2017-08-09 | Nichia Corporation | Method of producing a semiconductor device by bonding silver oxide on a surface of a semiconductor element with silver or silver oxide on a surface of a base |
| CN112967957A (en) * | 2021-02-07 | 2021-06-15 | 深圳市东飞凌科技有限公司 | Eutectic device and transistor packaging eutectic system |
| CN112967957B (en) * | 2021-02-07 | 2022-04-01 | 深圳市东飞凌科技有限公司 | Eutectic device and transistor packaging eutectic system |
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