JPS6047679B2 - Semiconductor memory inspection method - Google Patents

Description

[Detailed description of the invention] The present invention relates to a semiconductor memory testing method.

Demand for semiconductor memory has been increasing steadily in recent years, and this trend is expected to continue to increase in the future. Competition for semiconductor memory manufacturers to capture the market is becoming increasingly intense. There is. One way to capture the market is to supply low-priced products, but the yield rate in the diffusion process of semiconductor memory chips has a considerable impact on the final manufacturing price, and as memory capacity increases, this impact becomes more significant. It is expected that Therefore, even if the functional operation of all addresses is not necessarily normal depending on the application purpose or usage method for semiconductor memory users, if the number of defective addresses is significantly small compared to the memory capacity used, and the number of defective addresses is If a product can be used because its address is known in advance, it means that semiconductor memory, which was previously treated as a defective item if even one address is defective, regardless of the number of defective addresses, can also be used. This actually leads to an increase in the yield of non-defective products in the diffusion process, and ultimately allows the supply of lower-cost semiconductor memories. SUMMARY OF THE INVENTION An object of the present invention is to provide a testing method that allows such users to provide low-cost semiconductor memories.

According to the present invention, there is provided a semiconductor memory testing method characterized in that the quality of the memory under test is determined based on the number of defective addresses. In particular, according to the present invention, in a method for testing a semiconductor memory, the locations of defective addresses extracted from the functional test results of the memory under test are stored in a storage section within the testing device, the number of defective addresses is counted, and the The limit number of defective addresses set in the memory register is compared with the number of defective addresses of the memory under test, and the comparison circuit determines whether the number of defective addresses of the memory under test is greater than the limit number of defective addresses 5. An inspection method is obtained which is characterized in that items exceeding the value are judged as defective, and items not exceeding the value are judged as good. Hereinafter, one embodiment of the inspection method of the present invention will be specifically described with reference to the block diagram of FIG.
Register 14 before the test pattern is generated for a certain functional test.
A limit number of addresses is set in advance, and a test pattern is generated from the microprogram pattern generator 5 to transmit the address information to be tested to the x address decoder 3 and the Y address decoder 4 of the memory under test 1 (hereinafter referred to as MUT). give. At this time, address information corresponding to the MUT is also applied to the X address decoder 9 and Y address decoder 10 of the fail buffer memory 7 in the test equipment, and the MU
The output signal of Tl and the expected information generated by the pattern generator 5 are compared in a pass/fail judgment circuit 6, and if they match, the write operation of fail identification information is not performed to the fail buffer memory 7, but if they do not match. Fail identification information is written to the address of the fail buffer memory 7 corresponding to the address of MUTl by the write pulse signal generated by the defect judgment circuit 6. The above operation is repeated until the end of the test pattern, and after the end of the pattern, the x address decoder 9 and the Y address decoder 10 of the fail buffer memory 7 receive the address signal from the sequential address counter 11 by the same number of addresses as the tested MUT1. The limit set in advance in the register 14 is counted by the defect number counter 12 only when the output signal is a defective signal, and after the completion of the read operation for the specified number of addresses. The number of addresses and the count number of the counter 12 are compared by the count number comparison circuit 13, and if the count number is greater than the limit address number, the MUT1 is determined to be defective, and conversely, if the count number is equal or smaller than the limit number, the MUT1 is determined to be good. Next, an application example of a memory having a defective address stored by the inspection method of the present invention will be briefly described with reference to FIGS. 2 and 3.

If you are trying to create a memory system 15 with 64K words x 8 bits, if you want to create a memory system 15 with 4K words x 1 bit,
, the number of memories used would be 128 (Figure 2), but if we were to use 16K words x 1 bit memory 7 (Figure 3) and this memory 17 would be inspected by the inspection method of the present invention. However, if there are defective addresses scattered after the 13K word but it is determined to be good, this memory 17
At least? It can be used as a word x 1 bit memory, and therefore, if the memory system 15 is created using the memory 17, only 64 memories will be used as shown in FIG.

(Reference numerals 18 and 19 in the figure indicate the good address part and the bad address part.) This can reduce the area occupied by the memory of the printed board as is clear from comparing Fig. 2 and Fig. 3. If it is effective and the 16K memory 17 with defective addresses is cheaper than the 4K memory 16, further effects can be expected. Although the above description is one example of application, it is possible that the testing method of the present invention will be sufficiently effective with the development of other application examples, and can be applied to semiconductor memories in general.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the inspection method of the present invention. Figure 2 is an explanatory diagram of a memory system using a semiconductor memory of 16K words x 1 bit, and Figure 3 is an explanatory diagram of a memory system using a 16K word x 1 bit semiconductor memory.
FIG. 2 is an explanatory diagram of a memory system using a 1-bit semiconductor memory. 1 is a semiconductor memory under test (MUT), 2 is a memory cell section, 3 is an X address decoder, 4 is a Y address decoder, 5 is a microprogram pattern generator, 6
is a pass/fail judgment circuit, 7 is a fail buffer memory, 8 is a memory cell section, 9 is an X address decoder, 10 is a Y address decoder, 11 is a sequential address counter, 12 is a defect number counter, and 13 is a count comparison circuit. , 14 is a limit address number register, 15 is a memory system, 16 is a 4K word x 1 bit semiconductor memory, 17
is a semiconductor memory of 16K words×1 bit, 18 is a good address portion, and 19 is a bad address portion.

Claims (1)

[Claims] 1. In a method of testing a semiconductor memory, a storage section having a storage capacity equal to or larger than that of the memory under test is prepared, and the storage section is operated as described above by a selection signal for selecting a memory cell for testing the memory cell. a write step of selecting a memory under test in parallel and writing defective information to a corresponding address of the storage section when a defective cell is detected; and counting the number of defective addresses of the storage section after the writing step;
A comparison is made with a limit number of defective addresses set in advance in a resist to determine whether the number of defective addresses in the storage section is greater than the limit number of defective addresses, and based on the comparison result, it is determined whether the memory under test is good or defective. A semiconductor memory testing method characterized by: