JPS6042621B2 - MOS integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to MOS integrated circuits, and more particularly to self-back bias circuits thereof.

Although MOS integrated circuits are becoming more highly integrated and faster, especially in digital memories, they are still slower than bipolar integrated circuits.

The main reason for this is that the conductance of the MOS transistor is small, and it takes time to charge and discharge the capacitance of the load. Therefore, in the past, for example, in the case of an n-channel, a power supply of VDD=+5VNVss■ In addition to OV, VBB=-5V was prepared for so-called back bias, and VBB was applied to the substrate to increase the capacitance between the substrate and the source and drain. efforts were being made to reduce However, this method requires an external VBB terminal, which poses a problem in that high integration is hindered. Recently, as a MOS integrated circuit that solved this problem,
A self-back bias circuit integrated into an integrated circuit was announced (ISSCC76/THURSDAY, F
EB, 19, 197 Anti-SESS-IONXll MEM
ORYINTHRM12.6■A70-nsIKMOS
(See RAM).

The self-back bias circuit is constructed as shown in FIG. This is an example of an n-channel MOS transistor Q,,Q. an amplifier consisting of a MOS transistor Qa;
An approximately 1 MH2 oscillator α°C is configured by applying feedback, and its output is passed through a driver DR consisting of MOS transistors Q, , Q5 to a capacitance C and a MOS transistor Q. , Q, and the output end of this charge pump circuit CP is connected to the semiconductor substrate. With this configuration, now VDD■+5V. ．． If Vss=0V, driver D
As the output of R swings, MOS transistors Q5 and Q7 act as diodes, that is, as pump valves, and pump positive charges from the semiconductor substrate, thereby charging the substrate negatively. As a result, ■BB circle -2.5V is obtained at the output of the charge pump circuit CP, and the reference voltage ■Ss=
A voltage will be applied between it and 0V. Therefore, if the self-back bias circuit of FIG. 1 is used, VDD=+
A back bias is applied to each MOS transistor of the MOS integrated circuit using a single 5V power supply, and the capacitance between the substrate and the source and drain can be reduced.

Incidentally, in a MOS integrated circuit, it is preferable for the capacitance to be as small as possible in order to increase speed and reduce power consumption, and in this sense, it is preferable that the back bias be as large as possible without causing avalanche breakdown. However, in the circuit of FIG. 1, the back bias voltage VBB obtained when DD=+5V is only about 3V at most, which is still insufficient. This invention has been made in view of the above-mentioned points, and aims to provide a MOS integrated circuit device that improves the self-back bias circuit shown in FIG. 1 and enables even higher speed and lower power consumption. .

The present invention is characterized in that a high back bias voltage is obtained by providing multiple stages of charge pump circuits of self-back bias circuits. Here, the drive terminals of the multi-stage charge pump circuit are connected in common, and the output terminal of each stage is sequentially stacked as a reference potential terminal for charge pumping of the next stage. A load capacitance larger than the pumping capacitance is connected to the output terminal of each stage. FIG. 2 shows a self-back bias circuit according to an embodiment of the present invention.

2 is relative to FIG. 1; corresponding parts are designated by the same reference numerals as in FIG. 1, and a detailed explanation of the invention is omitted. In this example, a two-stage charge pump circuit C
Pl and CP2 are provided. That is, the first charge pump circuit CPl includes a pumping capacitance C1 and MOS transistors Q6 and Q7 as diodes.
, a second circuit similarly consisting of a pumping capacitance C2 and MOS transistors Q8 and Q9 as diodes.
The input terminals of the charge pump circuits CP2 are commonly connected, the output terminal of the first charge pump circuit CP1 is connected to the source of the MOS transistor Q8 of the second charge pump circuit CP2, and the output terminal is connected to the load capacitance C3.
A back bias voltage VBB is obtained by connecting the output terminal of the second charge pump circuit CP2 to the substrate via the reference potential ■Ss. In addition, MOS
Transistors Q2, Q3, and Q5 are depletion type MOS transistors, and the other MOS transistors are enhancement type MOS transistors when a back bias is applied.

In addition, the capacitances C1 to C3 are, for example, a so-called MOS transistor in which the source and drain of a depletion type MOS transistor are connected in common and the gate is used as one terminal and the gate as the other terminal.
Consists of capacitors. In this case, Cl and C2 may have almost the same size, and C3 is larger than them. Note that the output terminal of the second charge pump circuit is a terminal that ultimately applies the substrate bias potential VBB to the substrate, and naturally has a large load r capacitance. With this configuration, the power supply is now set to VDD=+5V. ．． The operation when V = 0V will be explained.

The oscillator 0CS oscillates at about 1 MHz, and its output is driven by the driver DR to obtain an amplified output of about 5V. The output of the driver DR drives the capacitance C1 of the first charge pump circuit CPl, and the MOS transistors Q6 and Q7 serve as pump valves to pump negative charge from the reference potential V = 0V. The output terminal of the charge pump circuit CPl is negatively charged. On the other hand, the driver DR also drives the second charge pump circuit CP2 at the same time. At this time, since the second charge pump circuit uses the output terminal of the first charge pump circuit as a reference potential terminal for charge pumping, the second charge pump circuit uses the output terminal of the second charge pump circuit CP2 as the reference potential terminal for charge pumping. charge more deeply negatively than the output end of the This results in
By connecting the output end of the second charge pump regeneration memory P2 to the board, a back bias of about VBB (-5V) is possible. Note that if the load capacitance C3 is small, the second
A sufficient amount of charge cannot be stored as a pumping source for the charge pump circuit CP2, resulting in poor pumping efficiency and inability to ensure the stability of the final substrate bias voltage. Therefore, this load gear capacitance C3 is equal to at least the pumping capacitors Cl and C2.
It is important that it is larger than . As described above, in this embodiment, the capacitance between the source, drain, and substrate of the MOS transistors constituting the integrated circuit is significantly reduced by the large back bias, and therefore the integrated circuit can be operated at higher speeds and with lower power consumption. It will be planned.

In addition, since the back bias voltage is large, the inversion voltage of the field region that separates MOS transistors increases, which improves the degree of integration of 1, and thins the 2-field oxide film, which improves the processing accuracy of photoetching and improves the processing accuracy of 3-substrates. Since the impurity concentration can be lowered, the capacitance between the source, drain and substrate can be further reduced. FIG. 3 shows another embodiment of the invention, in which a larger back bias voltage is obtained.

That is, in this embodiment, a pumping capacitance C4 and MOS transistors QlO, QlO are added to the circuit shown in FIG.
Adding a third charge pump circuit CP3 consisting of
A load capacitance C5 is provided between the output terminal of the second charge pump circuit CP2 and the output terminal of the first charge pump circuit. And a third charge pump circuit CP3
By connecting the output end of B to the board, back bias ■B
B is applied to the substrate. Note that the capacitances Cl, C2, and C3 may all have the same size, and the capacitances C3 and C5 are larger than the capacitances Cl, C2, and C4. If you do this, VBB-7.
A back bias voltage of 5V can be obtained, and the capacitance between the source layer source and drain and the substrate can be made smaller than in the circuit shown in FIG.

It goes without saying that this embodiment also provides the same effects as the previous embodiment. Note that the present invention is not limited to the embodiments described above. For example, in the embodiment, two stages and three stages of charge pump circuits are shown, but if it is desired to obtain a larger back bias voltage, the number of stages may be further increased. Furthermore, in the embodiment, a MOS capacitor was used as the capacitance, but
For example, it may be a capacitor in which first and second polycrystalline silicon electrodes are provided above and below an insulating film. The oscillator 0SC1 driver DR and the like are not limited to those of the embodiment, but may have other configurations. As explained above, according to the present invention, by providing multiple stages of charge pump circuits in the self-back bias circuit of a MOS integrated circuit, it is possible to achieve higher speed, lower power consumption, and higher integration of the MOS integrated circuit. I can do that.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a self-back bias circuit in a MOS integrated circuit, FIG. 2 is a diagram showing a self-back bias circuit of one embodiment of the present invention, and FIG. 3 is a diagram of a self-back bias circuit of another embodiment. There is a diagram showing this. 0SC...Oscillator, DR...Driver C
Pl, CP2, CP3...Charge pump circuit.

Claims (1)

[Claims] 1 has a self-back bias circuit including an oscillator and a multi-stage charge pump circuit driven by the output of the oscillator, and the multi-stage charge pump circuit has drive terminals of respective charge pump capacitances connected in common. , a MOS integrated circuit, characterized in that the output terminal of each stage is successively stacked as a reference potential terminal for charge pumping of the next stage, and a load capacitance larger than the pumping capacitance is connected to the output terminal of each stage. circuit device.