JPS6035551A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6035551A JPS6035551A JP59152903A JP15290384A JPS6035551A JP S6035551 A JPS6035551 A JP S6035551A JP 59152903 A JP59152903 A JP 59152903A JP 15290384 A JP15290384 A JP 15290384A JP S6035551 A JPS6035551 A JP S6035551A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- leads
- front ends
- resin
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体チップを固定するタブと、半導体チッ
プの各電極への入出力電気信号を導くための複数のリー
ドとから成るリードフレームを用いた半導体装置の製法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device using a lead frame consisting of a tab for fixing a semiconductor chip and a plurality of leads for guiding input/output electrical signals to each electrode of the semiconductor chip. .
レジンモールド型半導体装置、特にＩＣの場合、半導体
チップを固着するタブ部と多数のリードとを一体に形成
したリードフレームが使用される。In the case of resin molded semiconductor devices, particularly ICs, a lead frame is used in which a tab portion for fixing a semiconductor chip and a large number of leads are integrally formed.
表面を銀被覆したリードフレームを用いたレジン封止型
半導体装置が特開昭４９−１０６７２号に開示されてい
る。A resin-sealed semiconductor device using a lead frame whose surface is coated with silver is disclosed in JP-A-49-10672.
第１図は通常使用されるリードフレームの構造を示して
いる。ｌが半導体チップ８を固着するタブで、このタブ
は支持リード８により支持されている。タブ１の周囲に
は多数のアウターリード４があり、各アウターリードの
一端はインナーリード８に連続すると共に、各アウター
１１−ドの他端は外枠５に結合している。各インナーリ
ードと各アウターリードとの境界部付近にはタイバーと
呼ばれる連結部６が設けられており、各リードはこのタ
イバー６で橋絡、支持される。このタイバー６は各リー
ドを支持するのみならず、レジンモールドの際の樹脂の
流れを防止する作用がある。なお、外枠５にはガイド用
穴７が開けられている。FIG. 1 shows the structure of a commonly used lead frame. 1 is a tab for fixing the semiconductor chip 8, and this tab is supported by the support lead 8. There are a large number of outer leads 4 around the tab 1, one end of each outer lead is continuous with the inner lead 8, and the other end of each outer lead 11 is connected to the outer frame 5. A connecting portion 6 called a tie bar is provided near the boundary between each inner lead and each outer lead, and each lead is bridged and supported by this tie bar 6. This tie bar 6 not only supports each lead but also functions to prevent resin from flowing during resin molding. Note that a guide hole 7 is made in the outer frame 5.
上記の構造のリードフレームは、金属テープを打ち抜く
ことにより作られる。The lead frame having the above structure is made by punching out a metal tape.
さて、このリードフレームを使用してレジンモールド型
の半導体装置を製造する場合には、まずタブに半導体チ
ップ２をＡｕ−８ｉ共晶合金又は半田等のろう材を使用
して固着し、次いでチップ２の各電極と各インナーリー
ド８の先端部（ポスト部）とをＡｕ細線９で接続する。Now, when manufacturing a resin mold type semiconductor device using this lead frame, first, the semiconductor chip 2 is fixed to the tab using a brazing material such as Au-8i eutectic alloy or solder, and then the chip Each electrode of No. 2 and the tip (post portion) of each inner lead 8 are connected with a thin Au wire 9.
２のワイヤボンド後点線１０で囲まれた部分にモールド
金型を用いてレジンを付着させ、固化する。最後に各リ
ードと外枠及び各リードを橋絡するタイバーをそれぞれ
切断し、各リードを独立させて、レジンモールド型の半
導体装置、例えばレジンモールド型ＩＣ等を得る。After wire bonding in step 2, resin is applied to the area surrounded by the dotted line 10 using a mold and solidified. Finally, each lead, the outer frame, and the tie bar bridging each lead are cut, and each lead is made independent to obtain a resin molded semiconductor device, such as a resin molded IC.
ところで、最近ではレジンモールド型の半導体装置（Ｉ
Ｃ等）は、高密度、小型化の傾向にある。By the way, recently resin mold type semiconductor devices (I
C, etc.) are trending toward higher density and smaller size.
この小型化は、リードフレームの微細化を来たし、各リ
ードの寸法を必然的に微細化し、変形し易くする。また
、インナーリードを長くする必要がある場合などにもリ
ード変形が生じやすくなる。このようにリード変形が生
じ易くなると、特にインナーリードの先端部の位置精度
が低下し、ワイヤボンディングの成功率が著しく低下す
るという問題がある。This miniaturization leads to the miniaturization of the lead frame, which necessarily makes the dimensions of each lead smaller and easier to deform. Furthermore, lead deformation is likely to occur when the inner lead needs to be made longer. If lead deformation is likely to occur in this way, there is a problem in that the positional accuracy of the tip end of the inner lead in particular decreases, and the success rate of wire bonding decreases significantly.
ワイヤボンドかされるインナーリード先端部に変形が生
じない新規な構造のリードフレームを用いた半導体装置
の製法を提案するにある。The present invention proposes a method for manufacturing a semiconductor device using a lead frame with a novel structure that does not cause deformation of the tips of inner leads to which wire bonding is performed.
上記の目的を達するため、本発明は、これまでのタイバ
ーとは別にインナーリード先端部近傍にもリード連結部
を設けたことを特徴とするものである。In order to achieve the above object, the present invention is characterized in that, in addition to the conventional tie bar, a lead connecting portion is also provided near the tip of the inner lead.
本発明の実施例を第２図に基づき更に説明する。An embodiment of the present invention will be further explained based on FIG.
図中第１図と同一符号は同一部分を示している。In the figure, the same reference numerals as in FIG. 1 indicate the same parts.
又説明の都合上要部を拡大して示しである。本発明で特
徴とするところはアウターリード４とインナーリード８
との境界部に設けたタイバー６とは別にインナーリード
先端部近傍に連結部１１を設けたことにある。Also, for convenience of explanation, important parts are shown enlarged. The features of the present invention are the outer lead 4 and the inner lead 8.
In addition to the tie bar 6 provided at the boundary with the inner lead, a connecting portion 11 is provided near the tip of the inner lead.
第２図に示したリードフレームを利用して、レジンモー
ルド型のＩＣを製造する方法を以下に述べる。A method for manufacturing a resin mold type IC using the lead frame shown in FIG. 2 will be described below.
まずタブ１土にＡｕ−８ｉ共晶合金又は半田等を用℃・
てＩＣチップを固着し、次いでチップの各電極とインナ
ーリード先端部とをＡｕ細線９で接続し、その後連結部
１１をレーザービーム等で瞬時に溶断する。し７かる後
公知のトランスファモールド法でタブ、ＩＣチップ、
Ａ ｕ ａ＠、リード先端部をレジンモールドする。更
にタイバー６を分断して各リード８．４を独立させると
共に各り一部８．４をフレームから機械的切断により分
離し、レジンモールド型のＩＣを曲る。First, apply Au-8i eutectic alloy or solder to tab 1 soil at °C.
Then, each electrode of the chip and the tip of the inner lead are connected with a thin Au wire 9, and then the connecting portion 11 is instantaneously fused with a laser beam or the like. After that, the tab, IC chip,
A ua @, resin mold the lead tip. Further, the tie bar 6 is divided to make each lead 8.4 independent, and a portion of each lead 8.4 is separated from the frame by mechanical cutting, and the resin molded IC is bent.
本発明に用いたリードフレーム構造では、連結部１１に
よってインナーリード先端部が連結支持されているため
にワイヤボンドする際機械的強度が強く変形しにくく、
その位置精度は極めて良好である。その結果、インナー
リード先端部へのん線のワイヤボンドの成功率は高く、
また接着強度も強くレジンモールド中にボンド部が離れ
る事故は殆ど生じなくなった。In the lead frame structure used in the present invention, since the inner lead tips are connected and supported by the connecting part 11, the mechanical strength is strong and it is difficult to deform when wire bonding is performed.
Its positional accuracy is extremely good. As a result, the success rate of wire bonding the wire to the tip of the inner lead is high.
In addition, the adhesive strength is strong, and there are almost no accidents where the bonded part separates during resin molding.
本発明によれば、ワイヤボンティングの際リード先端部
の位置ずれかないため、重速ボンディングが可能となり
、レジンモールド型ＩＣの大量生産を歩留高（実現する
ことができる。According to the present invention, since there is no displacement of the lead tip during wire bonding, heavy-speed bonding is possible, and high yields can be achieved in mass production of resin molded ICs.
第１図は従来のリードフレームの構造を説明するための
平面図、第２図は本発明に係わるリードフレームの構造
を説明するための平面図である。
１・・・タブ、２・・・半導体チップ、３・・タブ支持
リード、４・・・アウターリード、５・・・外ｅ、６−
・・タイバー、８・・・インナーリード、１１・・・連
結部。
代毬へ 升埋士 高 橋 明 夫〜′−′第 １ 図
第 ２ 図FIG. 1 is a plan view for explaining the structure of a conventional lead frame, and FIG. 2 is a plan view for explaining the structure of a lead frame according to the present invention. DESCRIPTION OF SYMBOLS 1...Tab, 2...Semiconductor chip, 3...Tab support lead, 4...Outer lead, 5...Outer e, 6-
... Tie bar, 8... Inner lead, 11... Connection part. To Daimari, the masu buryer Akio Takahashi ~'-' Figure 1 Figure 2
Claims (1)
連結・支持する連結部を設けたリードフレームを準備す
る工程 ｔｂｌ 前記リードフレームのタブ上にチップを固着す
る工程 ｌｃｌ 前記チップの電極部と前記インナーリードとを
電気的に接続する工程 ｆｄｌ 前記連結部を除去する工程 ｔｅｌ 前記’）−ドフレームのタイバーの内側部分を
樹脂でモールドする工程 を有することを特徴とする半導体装置の製法。[Claims] 1. lal Step tbl of preparing a lead frame provided with a connecting part for connecting and supporting inner leads on the inside of the tie bar Step lcl of fixing a chip on the tab of the lead frame lcl A semiconductor device characterized by comprising the steps of electrically connecting the electrode portion and the inner lead, a step of removing the connecting portion, and a step of molding the inner part of the tie bar of the ')-deframe with resin. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59152903A JPS6035551A (en) | 1984-07-25 | 1984-07-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59152903A JPS6035551A (en) | 1984-07-25 | 1984-07-25 | Manufacture of semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7646178A Division JPS554908A (en) | 1978-06-26 | 1978-06-26 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6035551A true JPS6035551A (en) | 1985-02-23 |
Family
ID=15550649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59152903A Pending JPS6035551A (en) | 1984-07-25 | 1984-07-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6035551A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11022877B2 (en) | 2017-03-13 | 2021-06-01 | Applied Materials, Inc. | Etch processing system having reflective endpoint detection |
-
1984
- 1984-07-25 JP JP59152903A patent/JPS6035551A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11022877B2 (en) | 2017-03-13 | 2021-06-01 | Applied Materials, Inc. | Etch processing system having reflective endpoint detection |
| US12007686B2 (en) | 2017-03-13 | 2024-06-11 | Applied Materials, Inc. | Etch processing system having reflective endpoint detection |
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