JPS6030445B2 - automatic gain control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic gain control circuit for a reproduction output level of a digital magnetic recording device.

For example, an integrating circuit as shown in Fig. 1 is used in the gain detection section of the playback output level of a conventional digital magnetic recording device. In order to reduce errors in gain detection caused by instantaneous level fluctuations due to dust buildup or tape effects, the integration time constant can be made very large, but this will slow down the circuit's operation speed. However, it is limited by the need to adjust the gain within a certain fixed time.

Furthermore, this integration method has the disadvantage that errors occur during gain detection due to the waveform rate of the readout signal. The present invention eliminates all of the above-mentioned drawbacks, and uses a variable gain amplifier for the output signal amplifier, and employs a peak hold circuit in the gain control system of this amplifier. This method significantly reduces gain detection errors caused by level fluctuations in the circuit, increases the circuit's operating speed by reducing the charging time constant of the circuit, and also allows the control system to reset the hold voltage of the peak hold circuit. By employing a circuit having a set function, it is possible to quickly operate in the direction of lowering the gain.

In this way, by increasing the operating speed of the circuit, the accuracy of gain control can be increased, and gain control can be easily performed using a gain adjustment signal generated within a short time. To summarize the configuration of the present invention, the present invention provides an automatic gain control circuit for the reproduction output level of a digital magnetic recording device, which includes a variable gain amplifier that inputs a reproduction output voltage and outputs a gain-controlled output voltage; A peak hold circuit connected to the output side of the amplifier, and an upper limit voltage comparator that compares the voltage from this peak hold circuit with a preset upper limit voltage or lower limit voltage, respectively, and generates an output voltage when it deviates from the range. and a lower limit voltage comparator, a register that is connected to the upper and lower limit voltage comparators via a gate circuit and counts down or counts up according to the output pulse from the upper or lower limit voltage comparator, and DA converts to analog voltage to control variable gain amplifier
A timing pulse of a predetermined period that connects the converter and the gate circuit, and a reset pulse is sent by the peak hold circuit with a minute delay from this timing pulse, and output pulses from the upper and lower limit voltage comparators are both output. and a controller that stops sending out the reset pulse when it detects in synchronization with the timing pulse that the reset pulse has not been reset.

The present invention will be explained below by way of examples with reference to the drawings.

FIG. 2 is a block diagram of a circuit according to an embodiment of the present invention, FIG. 4 is an explanatory diagram of its operation, and FIG. 3 is a circuit diagram as an example of the peak hold circuit of FIG. 2.

In Fig. 2, 1 is the input terminal for the reproduction output signal of the digital magnetic recording device, and the waveform of the reproduction output signal inputted here is a high frequency constant amplitude waveform as shown by a in the top row of Fig. 4. , and this amplitude corresponds to the voltage level recorded on the magnetic tape.

The purpose of the present invention is to automatically adjust the gain of the amplifier so that when various amplitudes of this voltage level a are input, voltages of various amplitudes are output from the output side of the amplifier as described below. By doing this, the voltage level is maintained within a certain range. 2 in Figure 2 is the aforementioned variable gain amplifier, and from its output side, as shown in b in the second row from the top in Figure 4, when the input voltage level is low (on the left side), this Step up stepwise to adjust to a constant voltage bo, and when the input voltage level is high (on the right) step down stepwise to a constant voltage 〇. It is an attempt to adjust. Reference numeral 3 indicates an output terminal of the variable gain amplifier, which is connected to a rear stage on the reproduction side of the magnetic recording device.

4 is a peak hold circuit, an example of which is shown in FIG.

To explain Fig. 3, 21 is an operational amplifier which charges the capacitor 23 through the diode 22 when the voltage input to the decapod input terminal is higher than the voltage of the capacitor 23 connected to one input terminal. The voltage increases until it reaches the voltage input to the input terminal on the tenth side, but conversely, when the voltage on the tenth side becomes lower than the voltage on the one leg, the voltage of the capacitor 23 is cut off by the diode 22, so it does not discharge. The previous value is retained. Therefore, from the output state connected to the one side terminal, the peak value of the voltage input to the ten side input terminal is outputted. The third row c from the top of FIG. 4 shows the output voltage waveform from the peak hold circuit 4 mentioned above, which will be explained in detail later. This waveform is created by holding the peak value of . This voltage shown at c is then input to 5 and 6 in FIG. 2, where 5 is an upper limit voltage comparator and 6 is a lower limit voltage comparator. In the upper limit voltage comparator 5, as shown on the right side of FIG. occurs.
In the lower limit voltage comparator 6, as shown on the left side of FIG. Occur. Each output voltage of these upper limit voltage comparator 5 and lower limit voltage comparator 6 is connected to a separate gate circuit 8.
However, since the timing pulse sent from the controller 7 is input to the other input terminals of these gate circuits 8 and 9, the upper limit voltage comparison is performed from the gate circuits 8 and 9. A pulse in which the output voltages of the comparator 5 and the lower limit voltage comparator 6 are gated by a timing pulse is output. d in FIG. 4 indicates a timing pulse;
e is the output pulse from gate circuit 8, f is gate circuit 9
shows the output pulses from. These e and f signals are input to the register 10'.
In this case, when the e signal arrives, the register is counted down and the counted down digital signal, for example, a binary number, is output, and when the f signal arrives, the register is counted up and the counted up signal is output. For example, if you output a binary digital signal and convert it to the next D
Input to A converter 1 1. The OA converter 11 converts the input digital signal into an analog signal,
This analog-converted voltage is fed back to the variable gain amplifier 2 to change the amplification gain. In FIG. 4, i and i indicate an example of a binary digital output signal from the register 10,
k indicates an analog voltage output from the DA converter 10. On the other hand, the gate circuit 12 in FIG. is shown at h in FIG. 4, which is gated by the timing pulse only when no output voltage is sent from either the upper limit voltage comparator 5 or the lower limit voltage comparator 6.

Outputs a reset stop signal pulse. When this reset stop signal pulse h arrives, the controller 7 stops generating the timing pulse d and the reset signal pulse g. In this way, the output voltage of the variable gain amplifier 2 is automatically maintained within a constant voltage range. As described above, according to the present invention, since the peak hold circuit is connected to the output side of the variable gain amplifier, the output voltage of the peak hold circuit is maintained at the peak value even if the reproduction output level drops instantaneously. Since it continues as it is, there is no drop, and by setting the charging time constant of the peak hold circuit to a small value, it has high responsiveness to voltage increases in the playback output level, and the hold voltage of the peak hold circuit can be reset or set circuit. Since it is used, the long-range response to voltage drops in the reproduced output level is high, and therefore, the far-responsiveness to fluctuations in the reproduced output level as a whole is extremely high.Therefore, an accurate automatic gain control circuit can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a gain detection circuit for the reproduction output level of a conventional digital magnetic recording device, FIG. 2 is a circuit block diagram of an embodiment of the automatic gain control circuit according to the present invention, and FIG.
The figure shows an example of the peak hold circuit in Figure 2, and Figure 4 shows an example of the peak hold circuit in Figure 2.
The figure is an explanatory diagram of the operation of FIG. 2. The symbols used in the drawings indicate the following. 1...Control system input terminal, 2...Variable gain amplifier, 3...2
output terminal, 4...Peak hold circuit, 5.
... Upper limit voltage comparator, 6 ... Lower limit voltage comparator, 7 ... Controller, 8, 9, 12 ...
・Gate circuit, 10...Register, 11...
...DA converter, 21... Arithmetic circuit, 22.
...Diode, 23...Capacitor,
24...Reset transistor. Pig name: 3 images, 2 images, rare: 4 images

Claims (1)

[Claims] 1. In an automatic gain control circuit for the reproduction output level of a digital magnetic recording device, a variable gain amplifier that receives a reproduction output voltage and outputs a gain-controlled output voltage; a peak hold circuit connected to the output side of this amplifier; The voltage from the peak hold circuit is compared with a preset upper limit voltage or lower limit voltage, respectively, and an upper limit voltage comparator and a lower limit voltage comparator generate an output voltage when the voltage deviates from the preset range. a register connected to the upper and lower limit voltage comparators and counting down or counting up according to output pulses from the upper or lower limit voltage comparators; and converting a digital signal from this register into an analog voltage for controlling the variable gain amplifier. D
A converter, a timing pulse of a predetermined period for opening the gate circuit, and a reset pulse sent to the peak hold circuit with a minute delay from this timing pulse, and output pulses from the upper and lower limit voltage comparators are both output. and a controller that stops sending out the reset pulse when it detects in synchronization with the timing pulse that the reset pulse has not been reset.