JPS6028077A - Flag ram control circuit of pcm recording and reproducing device - Google Patents

Abstract

PURPOSE:To carry out the PQ correction with high efficiency and to improve the performance of a PCM recording/reproducing device by checking and correcting an error flag corresponding to the PQ correcting data word related to one data word of an RAM. CONSTITUTION:An output signal I2 of an address enable circuit 12 is supplied to an NAND circuit 16 together with a signal I3 of ''H'' obtained when no PQ correction is carried out. The output I5 of the circuit 16 controls the distribution of operation time of an RAM input circuit. An output circuit 13 counts error flag signals I13 of the PQ correcting data word given from a flag RAM2 and delivers a signal I19 of ''L'' only when just one error flag ''1'' exists with the P or Q series. Then the signal I3 of ''L'' is delivered as a correction timing command signal when both the signal I19 and the writing clock of the corrected data word are set at ''L''. The circuits 14 and 15 write an error flag to the RAM2 by the signal I3. At the same time, the circuit 16 attains the writing of the data word to be written to the same address as the RAM2 concurrently.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a decoder of a PCM recording/reproducing apparatus, and particularly to a flag RAM that stores an error flag indicating whether a data word is correct or incorrect.
The present invention relates to a control circuit for controlling the operation of a flag RAM in a decoder using a decoder.

[Backskin technology]

In a PCM recording and reproducing device, data recorded on a recording medium is a chain of formatted blocks.

For example, one block includes a block synchronization word (3 bits), a block address word (8 bits), an information word (8 bits x 8), a parity M (8 bits x 2), an error correction word (
ORCG) (16 bits). For example, one field is composed of 132 blocks.

Before extracting the data recorded according to the above format from the recording medium and reproducing it as an analog signal,
Detection of synchronization signals, conversion of serial data to parallel data (referred to as serial-parallel conversion), decoding of addresses, error checking (C
RC code, error correction, de-interleaving (before recording on the recording medium in the encoder, rearrangement of L as the burst code error pair, that is, interleaving is performed), based on the arrangement of the patterns performed in the decoder (referring to the return operation), etc. are performed. The part that performs these processes is called a decoder of the PCM recording and reproducing apparatus.

Conventionally, each of the above processes has been performed by sequentially passing through single-function circuits for each process, but such a system is inefficient as a whole decoder circuit, and the circuit configuration is complicated and difficult to manufacture. It wasn't easy.

Recently, an efficient decoder that uses RAM to perform input, output, and the above processing in parallel in a time-sharing manner has been proposed in a patent application filed by the same applicant entitled "Decoder for rPcM Recording and Reproducing Apparatus" (Japanese Patent Application No. 95486).

FIG. 1 is a block diagram schematically showing the configuration of such a decoder.

In FIG. 1, data RAM 1 is a RAM for storing data words (information words and parity blocks), and flag RAM 2 is a RAM for storing error flags indicating the degree of reliability of each data word. . Both RAMs 1 and 2 are given a common address by address circuit 3 and from address circuit 4 .

A signal 5 extracted from the recording medium is input to an input circuit 6. The input circuit 6 receives synchronization signals (field, block,
a synchronization extraction circuit which extracts the word) and sends it to the address generation circuit 3 via line 7, and a CR for the serial input signal.
An ORC circuit that performs a C check and stores the result in flag RAM2, and an ORC circuit that converts a serial signal into a parallel signal and stores the data R.
It includes a serial-to-parallel converter for sending data to the AMI data bus 8, a block address extraction circuit for extracting block addresses, and sending the extracted block addresses to an address generation circuit.

Simultaneously with the above input operation by the input circuit (time-divisionally in terms of RAM operation), data is output from the RAM.

Prior to output, the data is corrected by the PQ parity error correction circuit 9, and then deinterleaved by the address circuit before being output from the output circuit 10 to the D/A conversion circuit.

Data RAM 1 has a capacity to store three fields, and while inputting one field, outputting the other field.

In this way, once the data input to the decoder is
At the same time, an error flag indicating the reliability of the data obtained by the CRC check is stored in the flag RAM at the same address as the data, and then PQ parity error correction is performed.

For convenience of explanation, error correction II theory related to the present invention will be summarized here.

The theory of error correction using parity words P and Q is as follows.

The 8-bit data HRW00-WO7 and W10-W17 are respectively referred to as P-series and Q-series data words.

Parity P is W00+W01+W02'+WO3+WO4+WO5+
WO6+ WO7-P 00... (1) Parity Q is W10+W11+W12+W13+ P10+W14+
W15+W16+W1γ-QIO (2). However, plus is the addition of a+od 2.

From equations (1) and (2), becomes. however, It is.

Here, when there is one unreliable data word in each of the upper equation (P sequence) and the lower equation (Q sequence) of equation (3), error correction is possible. Assuming that example W12 is unreliable data, they are WO5', respectively.
It is assumed that W12' is shown.

At this time, if the error patterns are e05 and e12, it can be shown as follows.

From equations (3) and (4), W00+WO1+WO2+WO3+ POO-VO4
+ WO5' + WO6+ WO7-e05 ・--
---'(5)Q10+W10+W11+W12'+
W13+P10+W14+W15+W16+W1? -e
12 ・−・−(6) holds true.

Unreliable data W05 in P series and Q series respectively! and W12' are added to equations (5) and (6), respectively, (5) Samurai W 05' -e05 + W 05'-e
05 +e05 +WO5 W05 Formula (6) +W12' -e12 +W12'-a12
+e12 +W12 W12, and correct WO5 and W12 are obtained.

Based on the above theory, if we can point to unreliable data, we can correct it.

In the decoder to which the present invention is applied, data is input to the data RAM, and data R of the flag RAM is input to the data RAM.
The above reliability indication corresponding to each data is stored as an error flag at the same address as AM. If the error flag is "1", it indicates that the data word (byte) is unreliable; if it is "0", the data word is correct.

Based on the above theory, error correction is performed in the following steps.

(1) From data RAM1 (Figure 1), P-series data WOO, WOl, WO2, WO3, POO, WO4,
WO5°WOJ Read WO7 and perform exclusive OR. Q series data Q10. WlG, Wll, W1
2. W13. P.I.O.

W14. W15. WlG, W17. Exclusive OR is similarly performed for .

(2) Read the error flag from the flag RAM 2 (FIG. 1) at the same time as the data. If the error flag is [1], the corresponding data word is added to the result of section (1).
Add by 2 (exclusive OR).

(3) For each series of P and Q, count the number of error flags "1", and when the count value is 1, the error flag "1" is counted.
1'' address is replaced with the data obtained as a result of the above item (2), and the error flag is reset at that address. .

FIG. 2 shows one field of data input to the data RAM.

The 132 columns in FIG. 2 are blocks after the synchronization word, address word, and CRC candy are removed from each input block in the input circuit (6 in FIG. 1). L and R are information words, P.

Q indicates a parity word.

As shown in FIG. 2, error correction is performed on the fields stored in the data RAM 1 using the PQ correction data word. This method is illustrated in Figure 3.

FIG. 3(a) shows that the memory of the data RAM 1 is divided into three field areas. Figure 3 (
b) is a memory map in which the output portion of the entire memory area is enlarged. An example of the positional relationship of the data words of the P and Q series described above is shown by straight lines.

Generally speaking, data words and error flags are output for the first to ninth lines, and PQ correction is performed between them. Regarding the 10th line, the data word and error flag are output, and the error flag of the block in which the data word i is inserted between them is set to "1". This is to prevent the previous field's block from being output as correct and causing click noise when the next field is input and one block is skipped and stored due to synchronization. .

Executes the PQ correction operation as described above accurately and in a timely manner.
In order to do this, at the same time as reading the PQ correction data word,
Error flags are continuously output from the flag RAM, and their values (“
A control circuit is required that can quickly and accurately perform operations such as checking the number of error flags (1" or "0"), counting the number of error flags "1", and resetting the error flag after PQ correction.

[Disclosure of the invention]

An object of the present invention is to provide a flag RAM control circuit suitable for meeting the above-mentioned requirements.

The flag RAM full 1 circuit according to the present invention sets the error flag corresponding to the PQ correction data word to the flag RA at the same time as the data word for PQ correction is read from the data RAM.
An address enable circuit that enables reading from M and an error flag “1°” that corresponds to the PQ correction data candy.
, and if there is one 1" at the end of each of the P and N series, a signal for latching the data word and address corresponding to that "1" and executing P or Q correction. A flag RAM output circuit that outputs a flag RAM output circuit that confirms that the final block of the field is correct when the output signal from the flag RAM output circuit is received, when a correct PQ correction data word is input to the data RAM. When the last data word of each block is output from the data RAM, a flag ``0'' is input to the flag RAM, and 1'' is input to the flag RAM when the last data word of each block is output from the data RAM.
When the flag RAM input circuit that inputs the flag is under the same conditions as the flag RAM input circuit,
Flag RAIV that generates a built-in pulse in flag RAM
It is configured to include I-input i and lJ control circuits.

The flag RAM control circuit according to the present invention, when a data field once input to the data RAM is output in units of bytes in a time-sharing manner with the input, each time one data word is output, the data field is The error flag corresponding to the PQ correction data 1iI (see formula 3) related to
The flag is read from the RAM and inspected. error flag ″“
1'' is detected and a signal is generated. Count the number of error flags "1" for one series, and only when the count is 1, generate a command signal indicating the timing to correct the PQ correction data nod corresponding to the error flag "1'°. This command signal is supplied to the PQ correction circuit of the decoder and activates the correction operation at the appropriate time.

Further, the flag RAMllll1m circuit resets the error flag corresponding to the corrected data word to O''.

In addition to the above, the flag RAM i control circuit also performs the operations described above by ensuring that when the meridian data word for each block is output, the error flag corresponding to that block that becomes vacant is set to 1''. This eliminates the possibility of lick noise occurring.

As a result of the above, PQ correction is executed accurately, at the right time, and efficiently, which in turn contributes to improving the performance of the PCM recording/reproducing apparatus.

[Best mode for carrying out the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 4 is a circuit diagram showing the entire flag RAM control circuit according to the present invention together with data RAM related circuits.

The data RAM 1 and the flag RAM 2 are the same as those shown in FIG. 1; for example, the data RAM has a capacity of 4 bytes, and the flag RAM has a capacity of 4 bits.

Flag RAM! 11 The i11 circuit 11 includes an address enable circuit 12, a flag RAM output circuit 13, a flag RAM input circuit 14, and a flag RAM! includes a control circuit 15.

The address enable circuit 12 has PQ correction data g.
Allows access to the error flag of H. PQ
Correction data words W OO to WO7 and Q10 to W17
(See equation (.3) and FIG. 2) is read out to the PQ performance circuit (in the PQ parity error correction circuit 9 in FIG. 1). G5. G7
．． G8 is supplied to the address enable circuit 12.

Except for the last word of each block (line 10 in FIG. 2), signal G4 is Woo, G5 is W01 to WO7, G7 is Q10. G8 corresponds to W10 to W17, respectively. The waveforms and timing of these signals are shown in the timing chart of FIG. In FIG. 5, signal A15 is a reference block signal and has a frequency of, for example, 1.512 MHz. A frequency of 1/24 of this signal A15 (63
K Ilz ) is used for the output byte synchronization signal.

This is shown by signal G2.

In FIG. 4, a signal G10 is further applied to the address enable circuit 12 at the time of outputting a data word and an error flag, and a data word in the 10th row (see FIG. 2)
A signal G11 given at the time of output is supplied.

In addition to the above-mentioned signals, an address enable signal F input to the RAM is provided to the address enable circuit 12. During the period when this signal @F is active, data is being input to the data RAM, and during this period the flag RAM is
No output of M2 is performed.

FIG. 6 shows a detailed embodiment of the address enable circuit 12. Signal G4. G5. G7. G8. G10 and Gll are connected to the NAND circuit 121. As can be seen in Figure 5, if any of these input signals is LOW or "
O”), the output of the NAND circuit 121 is H (HI
GH or 1゛). This output signal 110 is supplied to the flag RAM output circuit 137\. The signal @110 is applied to the input of inverter 122, and inverter 122
The inverted signal 11 of 10 is output (see FIG. 5). This (11) is also supplied to the flag RAM output circuit 13. The output of the inverter 122 passes through three inverters 123 to provide a signal 12 (see FIG. 5) which is slightly delayed from the signal 110. This signal 112 is also the flag RA
is supplied to the M output circuit 13, and is also supplied to the NAND circuit 1.
24 inputs. The other one of the NAND circuit 124
A signal F is given as one input. Signal F is a signal that becomes H" only when data is input to data RAMI and flag RAM2, and becomes Bi at other times. Therefore, output signal 2 of NAND circuit 124 is a signal [ 12 inverted signals are given.

In Figure 4, the address enable circuit output signal ■
2 is input to the NAND circuit 16 together with a signal I3 (described later) which is ``H°'' □ when PQ correction is not performed, and as a result, from the NAND circuit 16, the address bus is used for RAM output. A signal (5) indicating that the vehicle is present is output. This signal I5 is supplied to the RAM input circuit (see FIG. 1) to control the operating time allocation of the input circuit.

Next, the flag RAM output circuit 13 outputs the flags RA~1.
, the message representing the error flag of the PQQ normal data word @
113, and count 1'' of those error flags. Then, in each P or . series, a belief that becomes “[” only when there is one error flag “1” @119
Output.

In FIG. 5, error flag '1' is shown in P series.
'' is one, whereas in the Q series there are two.

In FIG. 4, the output signal 119 of the flag RAM output circuit 13 becomes one input of the OR circuit 17. OR circuit 1
Another input of 7 is the output of an AND circuit 18 which obtains the AND of signals G6 and G9. Trust@G6 and G9
are the clock signals for writing corrected data words in the P and Q sequences, respectively. OR circuit 17
outputs a signal I3 which becomes ll L 11 when the signals 119, G6 and G9 are all 11111 (see FIG. 5).

FIG. 7 shows an embodiment for realizing the flag RAM output circuit 13 having the above-mentioned functions.

The error flag signal 113 from the flag RAM 2 is input to the AND circuit 131 together with the signal 112 supplied from the address enable circuit 12. The output signal 114 from the AND circuit 131 is connected to the flip-flop 1320 at J-.
This is one clear input.

J-, the flip-flop 132 uses 110 as a clock pulse, and when the signal 114 becomes "1", the output signal ■4
issue. Signal I4 is a signal indicating an error in the PQ correction data word, and can be used in the PQ correction circuit.

Flip-flop 132 on J- also outputs signals G6 and G9.
The signal 116 from the NANO circuit 133 which inputs is used as a clock pulse, and the signal G4 and -G7 are input
The output signal 115 of the AND circuit 134 is used as a clear input, and a signal 117 is supplied to the clear input of the 111 IT counter 135. The 1n counter 135 is supplied with the signal @[11 from the address enable circuit 12 (Fig. 4) as a clock pulse, and the output signal 113 of the flag RAM 2 as the P enable signal and the signal @G24 as the T enable signal. It is given. This signal G24
is a signal that becomes "L" when the last data word of the block (line 10 in FIG. L″ only when there is one 1″ in
A signal 119 (see FIG. 5) is obtained.

In FIG. 4, as described above, the output signal 119 of the flag RAM output path 13 and the clock signals G6 and 1G9 for correcting the P and Q sequences are input, and the A
The signal I3 detected by the ND circuit 18 and the OR circuit 17 is an error (error flag 1''). Since there is only one PQ correction data word in the P or Q sequence and it can be corrected, it is corrected. This is a signal that instructs the correct timing. In Fig. 5, the P sequence has one error word and can be corrected, whereas the Q sequence has two error words, so the This example shows that no pulse is generated and cannot be corrected.

This signal I3 is supplied to the flag RAM input circuit 14 and the flag RAM write control circuit 15, and is also supplied to the data RAM self-write control W port 16.

Next, the flag RAM input circuit 14 supplies a control signal 120 to the flag RAM 2 so that error flags corresponding to the following cases are input to the flag RAM 2.

(1) When a correct data word is input, an error flag "0" is input by signal H2.

(2) When the data of the last block is correct, signal H1
Input the error flag "0".

(3) When error correction in P and Q sequences is completed,
The error flag "0" is input by the signal I3.

(4) When the last data word of the block is output, the error flag "1" is input by the signal @G23 indicating this.

An 88th embodiment of the flag RAM input circuit 14 that performs the functions described above is shown. In this embodiment, a bus buffer 141 was used. The path buffer 141 is
When any of the C inputs (1 to 4) becomes °['', the six inputs with the same number (all are grounded) have the property of transferring it to the Y output with the same number. It can easily perform the functions in the above four cases.OR
Circuits 142 and 143 are input circuits (first
This is a circuit for preventing the bus buffer 141 from operating by signals G23 and G13 during operation 6) in the figure.

Next, the flag RAM in Figure 4! The write control circuit 15 supplies a signal 123 that enables writing of the flag RAM 2 when similar signals H1, H2, G23.13 are input under the same conditions as the flag RAM input circuit 14.

An example of such a circuit is shown in FIG. Further, a waveform diagram illustrating the operation of FIG. 9 is shown in FIG. 10.

While referring to FIGS. 9 and 10, flag RAtv1m
The integrated control circuit will be explained.

Error flag 110 when correct data word is input
Signal @H2 to input IT and signal 1 to input error 7 lag pa 0'' when the last block is correct.
1 and when the last open signal of the block is output, the output of the NAND circuit 151 is H'', and the output signal 121 is as shown in Figure 10.NAND circuit 151
output signal I21 and the signal for commanding the PQ correction mentioned above.
3 is input to the NAND circuit 152, so that the output of the NAND circuit 152 is the 10th inverted signal.
A signal 122 as shown in the figure is obtained.

The signal 122 is applied to one input of an OR circuit 155 and is also applied to an exclusive OR circuit 153 via a resistor 154.
is input. The output of the exclusive OR circuit 153 whose other inputs are 0 (ground) has a waveform of a signal! This signal is the same as 22 but is slightly delayed, and is applied to the other input of the OR circuit 155. Therefore, a narrow signal 123 shown in FIG. 10 is obtained as the output of the OR circuit.

As mentioned above, the write control circuit 16 of the data RAM uses a signal that enables the self-write operation of a data word to be written to the same address simultaneously with the flag RAM! 23 to data RA
Supply to M.

With the configuration of the flag RAM 1lII11 circuit as described above, when outputting a data word, error correction is performed using P and Q parities, and input/output of error flags corresponding to each data is performed with accurate timing. be able to. Furthermore, since each circuit can be easily constructed, manufacturing is also easy.

[Brief explanation of the drawing]

FIG. 1 shows a PC including data RAM and flag RAM.
FIG. 2 is a block diagram schematically showing the entire decoder of the M recording/reproducing device. The second view is a memory map showing the arrangement of data words stored in the data RAM. FIG. 3 is a memory map of the data RAM showing the positional relationship of PQ correction data. FIG. 4 shows the flag RAM ill 10 according to the present invention.
FIG. 1 is a circuit diagram showing an example of a circuit. Figure 5 shows the main points in Figure 4, signal 0)
It is a timing chart showing waveforms and timing. FIG. 6 is a circuit diagram showing details of the address enable circuit of FIG. 4. FIG. 7 is a circuit diagram showing details of the flag RAM output circuit in FIG. 4. FIG. 8 is a circuit diagram showing details of the flag RAM input circuit in FIG. 4. Figures 9 and 10 are shown in Figure 4.
2 is a circuit diagram showing details of the M write control circuit and a timing chart of signals of each part. 1...Data RAM. 2...Flag RAM. 12...Address enable circuit, 13...
. . . Flag RAM output circuit, 14 . . . Flag RAM input circuit, 15 . . . Flag RAM write control circuit. Applicant NEC Home Electronics Co., Ltd. Agent Patent Attorney Masu 1) Takeo

Claims (1)

[Claims] 1. The input data words from the recording medium are once stored in the data RAM.
In a decoder of a PCM recording and reproducing apparatus, the error flag representing the correctness of each data word is stored in the same address as the data RAM of the flag RAM, and the PCM recording and reproducing apparatus performs error correction using PQ parity and outputs the error flag. , a circuit for controlling the operation of the flag RAM, which makes it possible to read the error flag corresponding to the data word from the flag RAM at the same time as the data word for PQ correction is successively outputted from the data RAM. Address enable circuit and error flag 111 corresponding to the PQ correction data word.
Count the number of ITs, and if there is one 1'' at the end of each P sequence and Q sequence, latch the data word and address corresponding to that 1 and perform P or Q correction. a flag RAM output circuit that outputs a signal for the PQ correction; and when the output signal from the flag RAM output circuit is received, when a correct PQ correction data word is input to the data RAM, and when the last block of the field is When the correctness is confirmed, a flag ``0'' is input to the flag RAM, and when the last data word of each block is output from the data RAM, a 1 is input to the flag RAM.
'' under the same conditions as the flag RAM input circuit and the flag RAM input circuit,
Flag RAMt that generates write pulses for flag RAM
1. A flag RAM i control circuit for a PCM recording and reproducing apparatus, characterized in that it includes an i-input control circuit.