JPS6027458U - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6027458U JPS6027458U JP11975883U JP11975883U JPS6027458U JP S6027458 U JPS6027458 U JP S6027458U JP 11975883 U JP11975883 U JP 11975883U JP 11975883 U JP11975883 U JP 11975883U JP S6027458 U JPS6027458 U JP S6027458U
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- recess
- ceramic layer
- semiconductor element
- semiconductor equipment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図および第２図は従来の光結合半導体装置を示す断
面図、第３図はこの考案の半導体装置の第１の実施例を
示す断面図、第４図はこの考案の第２の実施例を示す断
面図、第５図はこの考案の第３の実施例を示す斜視図で
ある。
２１・・・セラミック層、２２・・・凹部、２３・・・
半導体発光素子用導体パターン、２４・・・絶縁層、２
５・・・半導体受光素子用導体パターン、２６・・・半
導体発光素子、２７・・・ワイヤ、２８・・・半導体受
光素子、２９・・・ワイヤ、３０・・・バンプ電極。1 and 2 are sectional views showing a conventional optically coupled semiconductor device, FIG. 3 is a sectional view showing a first embodiment of the semiconductor device of this invention, and FIG. 4 is a sectional view showing a second embodiment of this invention. FIG. 5 is a sectional view showing an example, and FIG. 5 is a perspective view showing a third embodiment of the invention. 21... Ceramic layer, 22... Concave portion, 23...
Conductor pattern for semiconductor light emitting device, 24... Insulating layer, 2
5... Conductor pattern for semiconductor light receiving element, 26... Semiconductor light emitting element, 27... Wire, 28... Semiconductor light receiving element, 29... Wire, 30... Bump electrode.
Claims (1)
ク層からなるセラミックパッケージと、前記凹部内から
それ以外の平坦部表面に延びて前記セラミック層に形成
された第１の導体パターンと、この第１の導体パターン
と絶縁して前記セラミック層の平坦部表面に形成された
第２の導体パターンと、前記第１の導体パターンに電気
的に接続されて前記セラミック層の凹部内に設けられた
第１の半導体素子と、この第１の半導体素子と対向する
ように前記凹部の開口部上に設けられ、前記第２の導体
パターンと電気的に接続される第２の半導体素子とを具
備してなる半導体装置。A ceramic package consisting of a single layer of ceramic layer in which a recess with a sloped side surface is processed into a predetermined portion; a first conductor pattern extending from the inside of the recess to the surface of the other flat part and formed on the ceramic layer; a second conductor pattern formed on the flat surface of the ceramic layer insulated from the first conductor pattern; and a second conductor pattern electrically connected to the first conductor pattern and provided in the recess of the ceramic layer. The device includes a first semiconductor element, and a second semiconductor element provided on the opening of the recess so as to face the first semiconductor element and electrically connected to the second conductor pattern. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11975883U JPS6027458U (en) | 1983-08-02 | 1983-08-02 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11975883U JPS6027458U (en) | 1983-08-02 | 1983-08-02 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6027458U true JPS6027458U (en) | 1985-02-25 |
Family
ID=30274724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11975883U Pending JPS6027458U (en) | 1983-08-02 | 1983-08-02 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6027458U (en) |
-
1983
- 1983-08-02 JP JP11975883U patent/JPS6027458U/en active Pending
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