JPS60261164A - Manufacture of groove type mos capacitor - Google Patents

Abstract

PURPOSE:To form a groove type MOS capacitor simply, by forming a groove of the capacitor in a silicon substrate, and sequentially forming a silicon oxide film and a conductive layer in the groove. CONSTITUTION:A high concentration N-type impurity introduced region 22 is formed on a silicon substrate 11 by using a mask 13. A groove 3 for forming a capacitor, which penetrates through the impurity introduced region 22, is formed. Then, the mask 13 is removed. Thereafter, a silicon oxide film 4 is formed on the entire surfaces of the substrate 11 and the silicon oxide film 4 by thermal oxidation processing. Then, a conducting layer 5 having a required pattern is formed on the silicon oxide film 4. Thus the groove type MOS capacitor can be manufactured by simple processes.

Description

Detailed Description of the Invention: Industrial Field of Application The present invention has a silicon substrate in which a capacitor forming groove is formed from the main surface side, and a silicon substrate having a continuous groove formed on the main surface side and the inner surface side of the capacitor forming groove. A trench type MOS having a structure in which an extending silicon oxide film is formed as an insulating film, and a conductive layer is formed on the silicon oxide film.
Concerning improvements in capacitor manufacturing methods.

2. Description of the Related Art Conventionally, as the above-mentioned trench type MOS capacitor, one having the structure described below with reference to FIG. 2 has been proposed.

That is, it has a silicon substrate 1.

A capacitor formation groove 3 is formed in this silicon substrate 1 from the main surface 2 side.

Thus, a silicon oxide film 4 containing 3iQ2 as a main component is formed as an insulating film, continuously extending to the main surface 2 side of the silicon substrate 1 and to the inner surface side of the capacitor formation groove 3. A conductive layer 5 made of polycrystalline silicon doped with impurities such as phosphorus and arsenic is formed on the film 4 .

The above is the structure of the conventionally proposed trench type MOS capacitor.

According to the trench type MOS capacitor having such a configuration, the area between the silicon substrate 1 and the conductive layer 5 is determined according to the area of the region of the silicon oxide film 4 where the silicon substrate 1 and the conductive layer 5 face each other. Although it is clear that it exhibits a capacity,
In this case, the silicon oxide film 4 extends along the capacitor forming groove 3 of the silicon substrate 1, and the conductive layer 5 extends over the extended region, so that the same capacitance can be applied to the silicon substrate 1 as a capacitor. Compared to a trench type MOS capacitor having a structure in which the formation trench 3 is not provided, a silicon oxide H4 is formed on the main surface 2 of the silicon substrate 1, and a conductive layer 5 is formed on the silicon oxide film 4. However, it has the characteristic that it can be obtained with a small area of the silicon substrate 1.

As a method for manufacturing a trench type MOS capacitor similar to the trench type MOS capacitor having such characteristics, a method described below with reference to FIG. 3 has been proposed. In FIG. 3, parts corresponding to those in FIG. 2 are designated by the same reference numerals.

That is, an original silicon substrate 11 having a flat main surface 12, which will later become the silicon substrate 1 described above in FIG. 1, is prepared in advance (FIG. 3A).

Then, on the main surface 12 of the original silicon substrate 11, a mask layer 13 made of, for example, 5102, having a pattern corresponding to the capacitor forming groove 3 described above in FIG. (FIG. 3B).

Next, capacitor formation grooves 3 are formed in the original silicon substrate 11 by etching such as reactive ion etching using the mask layer 13 as a mask for the original silicon substrate 11 (FIG. 3C).

Next, the mask layer 13 is removed from the main surface 12 of the original silicon substrate 11 using, for example, a buffered hydrofluoric acid solution, and thus the capacitor forming groove 3 is formed from the main surface 2 side of the original silicon substrate 11. Obtain the formed silicon substrate 1 (Fig. 3D)
.

Next, the silicon substrate 1 is subjected to a thermal oxidation treatment to form a silicon oxide film 4 that continuously extends on the main surface 2 side of the silicon substrate 1 and on the inner surface side of the capacitor forming groove 3 (FIG. 3E).

Next, on the silicon oxide film 4, a conductive layer 5 made of polycrystalline silicon into which impurities such as phosphorus and arsenic are introduced is formed.
are formed into a desired pattern, including a step using, for example, a low pressure CVD method using silane (FIG. 3F).

Including the above steps, a trench type MOS capacitor similar to the trench type MOS capacitor described above in FIG. 2 is manufactured.

The above is the groove type M described above in FIG. 2 that has been proposed in the past.
This is a method for manufacturing a trench type MOS capacitor similar to an OS capacitor.

According to the manufacturing method of such a trench type MOS capacitor, the steps of preparing a silicon substrate 1 in which a capacitor formation trench 3 is formed from the main surface 2 side (FIGS. 3A to 3D), and By the oxidation treatment, the silicon substrate 1
The step of forming a silicon oxide film 4 as an insulating film that extends continuously on the main surface 2 side and the inner surface side of the capacitor forming groove 3 (FIG. 3E), and forming a conductive film on the silicon oxide film 4 (FIG. 3E). A trench type MOS capacitor similar to the trench type MOS capacitor described above in FIG. 2 can be manufactured by a simple process including the step of forming layer 5 (FIG. 3F).
It has the following characteristics.

Problems to be Solved by the Invention However, in the case of the conventional trench type MOS capacitor manufacturing method described above in FIG. 3, in the step of forming the silicon oxide film 4 (FIG. 3F), the silicon oxide film 4 teeth,
The silicon oxide film 4 is usually formed by thermal oxidation treatment at a temperature of 900°C to 1000°C, and in this case, the silicon oxide film 4 covers the area on the open end side of the capacitor forming groove 3 of the silicon substrate 1. [14 and area 1 on bottom side area 15
6 and 17 are formed to have a thinner thickness than other regions. In particular, the region 16 on the open end side region 14 of the capacitor forming groove 3 of the silicon substrate 1 is formed to have a significantly thinner thickness.

For this reason, when the silicon oxide film 4 is formed to have a small thickness in order to manufacture a trench type MC)S capacitor with a large capacity, the trench type MOS capacitor must be manufactured to have a high breakdown voltage. It had the disadvantage that it could not be done.

Furthermore, in the case of the conventional trench type MOS capacitor manufacturing method described above with reference to FIG. If the silicon oxide film 4 is formed by the thermal oxidation treatment described above, the silicon oxide film 4 is formed in the regions 16 and 17 on the open end side region 14 and bottom side region 15 of the capacitor formation trench 3 of the silicon substrate 1. 90
The silicon oxide 1114 can be formed to have a thicker thickness than the case where it is formed by thermal oxidation treatment at a temperature of 0° C. to 1000° C. regions 16 and 17 on the open end side region 14 and bottom side region 15 of the forming groove 3;
It can be formed so that there is only a slight difference between it and other regions.

However, when elements such as transistors are formed on the silicon substrate 1, if the silicon oxide film 4 is formed by high temperature thermal oxidation treatment as described above,
The high temperature heat deteriorates the characteristics of the elements formed on the silicon substrate 1 or damages them.

By means of solving the problem, the present invention provides a novel channel MO without the above-mentioned drawbacks.
This paper aims to propose a manufacturing method for S capacitors.

According to the manufacturing method of the trench type MOS capacitor according to the present invention Box 1 and the second invention, the conventional trench type MOS capacitor described above in FIG.
As in the case of the capacitor manufacturing method, the silicon substrate in which the capacitor formation groove is formed is prepared from the main surface side, and the silicon substrate is oxidized to form the main surface side of the silicon substrate and the capacitor formation groove. A trench type MOS capacitor is manufactured by including the steps of forming a silicon oxide film continuously extending to the sides as an insulating film, and forming a conductive layer on the silicon oxide film.

However, in the method for manufacturing a trench type MOS capacitor according to the first invention of the present application, in the step of preparing a silicon substrate, at least the region on the open end side of the capacitor forming trench is separated from other regions. In contrast, it is assumed that a high concentration N-type impurity introduced region is subjected to accelerated oxidation.

Further, in the case of the method for manufacturing a trench type MOS capacitor according to the second invention of the present application, in the step of preparing a silicon substrate,
The silicon substrate is made of a high-concentration N type in which at least the region on the open end side of the capacitor formation trench and at least the region on the bottom side of the capacitor formation trench are oxidized at a faster rate than other regions. It is prepared as if it had been done in the impurity introduction region.

Effect - Therefore, according to the method for manufacturing a groove-type MoS capacitor according to the first invention of the present application, in the step of forming a silicon oxide film, the silicon oxide Il! Even if i14 is not subjected to thermal oxidation treatment at high temperatures, there is almost no difference in thickness between the region on the open end side of the capacitor formation groove of the silicon substrate and the other regions. It can be easily formed as a device that does not have a , but even if it does, there is only a slight difference.

Further, according to the method for manufacturing a trench type MOS capacitor according to the second invention of the present application, in the step of forming a silicon oxide film, the thickness of the silicon oxide film 4 is adjusted to the opening of the trench for forming a capacitor in the silicon substrate. To be easily formed so that there is almost no difference or only a small difference between the areas on the end side and bottom side and other areas. I can do it.

As a result of the effects of the invention, a trench-type MOS capacitor having a large capacitance can be obtained by both the method for manufacturing a trench-type MOS capacitor according to the first invention of the present application and the method for manufacturing a trench-type MOS capacitor according to the second invention of the present application. Even if the silicon oxide film is formed to a thin thickness in order to manufacture the capacitor, it has a higher withstand voltage than the trench MOS capacitor obtained by the conventional trench MOS capacitor manufacturing method described above in FIG. It has the characteristic that it can be easily manufactured.

Embodiment 1 First, an embodiment of a method for manufacturing a trench type MOS capacitor according to the first invention of the present application will be described with reference to FIG.

In FIG. 1, parts corresponding to those in FIG. 3 are given the same reference numerals and detailed explanations are omitted.J The method for manufacturing the trench type MOS capacitor according to the first invention of the present application shown in FIG. 1 will be described below. Taking the sequential steps, the second
A groove-type MOS capacitor 1--<-> is manufactured similar to that described above with reference to the figures.

That is, as described above in FIG. 3A, the flat main surface 1
Prepare in advance an original silicon substrate 11 having a
Figure A).

Then, a mask layer 13 is formed on the main surface 12 of the original silicon substrate 11 in the same manner as described above with reference to FIG. 3B.
Figure 1B).

- Next, by introducing an N-type impurity such as phosphorus or arsenic into the original silicon substrate 11 using the mask layer 13 as a mask, a region of the mask layer 13 facing the window 21 and connected thereto is introduced into the original silicon substrate 11. It is continuous with the region under the mask layer 13 up to a position slightly distant from the window 21, and is 2×1°019 to 3 in terms of surface impurity concentration.
A heavily doped N-type impurity region 22 having a high N-type impurity concentration of 0.times.10 atOm/Cm3 is formed (FIG. 1C).

In this case, the N-type impurity introduction process into the original silicon substrate 11 may be performed by injecting N-type impurity ions into the original silicon substrate 11 and then performing heat treatment in an inert gas atmosphere, for example. , arsenic ions accelerated to 100 KeV were implanted at a dose of 4 x '1015 cm-2,
The process may be such that it is implanted into the original silicon substrate 11 and then heat-treated at 1000° C. for 60 minutes in a nitrogen atmosphere. In addition, the N-type impurity introduction treatment is, for example, POCl
It is also possible to perform a vapor phase diffusion treatment using 2.

In addition, as shown in the first diagram, the N-type impurity introduction treatment is carried out on a region of the mask layer 13 of the original silicon substrate 1 facing the window 21 and on the mask layer 13, such as a phosphorus silicate glass, which is continuously extended. N-type impurity-containing layer 2 made of (PSG)
3 can be formed by a deposition process, and then an N-type impurity is introduced into the original silicon substrate 11 from the N-type impurity-containing layer 23 by a heat treatment.

Next, the original silicon substrate 11 is etched using the mask layer 13 as a mask.
When an N-type impurity-containing layer 23 is used in the N-type impurity introduction process as shown in the first diagram, the process is performed after removing the N-type impurity-containing layer 23.
In the region facing the window 21 of the mask layer 13, a capacitor formation groove 3 having a pattern corresponding to the window 21 is formed, and a high concentration N-type impurity doped region 22 is formed.
From this, a heavily doped N-type impurity region 24 is formed in the region 14 on the open end side of the capacitor forming groove 3 of the original silicon substrate 11 (FIG. 1E).

In this case, the etching process for the original silicon substrate 11 may be a known reactive ion etching process, for example, CBrF3 gas ions at a pressure of 1'4 m t Or r excited by a high frequency of 0.1 W/cm2. It can be a treatment using

Next, the mask layer 13 is formed in the same manner as described above in the third diagram.
Remove from the main surface 12 of the original silicon substrate 11, or
A capacitor forming groove 3 is formed from the main surface 2 side of the original silicon substrate 11, and a capacitor forming groove 3 is formed from the main surface 2 side.
A region 14 on the open end side of the high concentration N-type impurity doped region 2
4 (FIG. 1F). Next,
By thermal oxidation treatment on the silicon substrate 1, the silicon oxide 11!4 continuously extending to the main surface 2 side of the silicon substrate 1 and the inner surface side of the capacitor forming groove 3 is removed by 50 or more people.
Form to a thickness of 1,000 people (Figure 1G).

In this case, the thermal oxidation treatment for the silicon substrate 1 may be thermal oxidation treatment at a temperature of 900° C. to 1000° C. using a dry oxygen atmosphere. In such a case, the silicon oxide film 4 may be added to the high concentration N-type impurity doped region 24 of the silicon substrate 1.
Region 1 on the open end side of the capacitor forming groove 3
4, since the region 14 is a high-concentration N-type impurity introduced region 24, it is formed at twice the rate of formation on other regions. The region fii! on the region 14 on the open end side of the capacitor forming groove 3 of the substrate 1! 16 and the other regions, there may be little difference or only a small difference.

Next, a conductive layer 5 is formed in a desired pattern on the silicon oxide film 4 in the same manner as described above with reference to FIG. 3F (FIG. 1H).

Including the above steps, a trench type MOS capacitor similar to the trench type MOS capacitor described above in FIG. 2 is manufactured.

The above is an embodiment of the method for manufacturing a trench type MOS capacitor according to the first invention of the present application.

According to the embodiment of the method for manufacturing a groove type MOS capacitor according to the first invention of the present application, the capacitor forming groove 3 is formed from the main surface 2 side, and the open end side of the capacitor forming groove 3 is formed from the main surface 2 side. A process of preparing a silicon substrate 1 in which the region 14 is made into a high-concentration N-type impurity-introduced region that is oxidized at a faster rate than other regions (FIGS. 1A to 1F) and an oxidation treatment for the silicon substrate 1. , a step of forming a silicon oxide film 4 as an insulating film that continuously extends on the main surface 2 side of the silicon substrate 1 and on the inner surface side of the capacitor forming groove 3 (FIG. 1G), and the silicon oxide film 4 It is said that it is possible to manufacture a trench type MOS capacitor similar to the trench type MOS capacitor described above in FIG. Has characteristics.

Moreover, the groove-type MO according to the first invention of the present application shown in FIG.
According to the manufacturing method of the S capacitor, in the step of forming the silicon oxide film 4, the thickness of the silicon oxide film 4 can be reduced to the same thickness as that of the capacitor formed on the silicon substrate 1, without having to undergo thermal oxidation treatment at high temperatures. Region 14 on the open end side of the groove 3
The upper region 16 and the other regions can be easily formed so that there is almost no difference, or even if there is, only a small difference.

Therefore, even if the silicon oxide film 4 is formed to have a small thickness in order to manufacture a trench type MOS capacitor with a large capacitance, the trench type MOS capacitor cannot be manufactured using the conventional method described above in FIG. It has a feature that it has a higher breakdown voltage than a trench MOS capacitor obtained by a trench MOS capacitor manufacturing method and can be manufactured easily.

Embodiment 2 Next, a first embodiment of a method for manufacturing a trench type MOS capacitor according to the second invention of the present application will be described with reference to FIG.

In FIG. 4, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The method for manufacturing a trench type MOS capacitor according to the second invention of the present application shown in FIG.
A trench type MOS capacitor similar to that described above in the figures is manufactured.

That is, by performing the steps described above with reference to FIGS. 1A to 1E, the mask layer 13 is formed on the original silicon substrate 11, and the capacitor forming groove 3 is formed in the original silicon substrate 17 using the mask layer 13 as a mask. After obtaining a configuration in which the region 14 on the open end side of the capacitor formation groove 3 of the original silicon substrate 11 is made into the high concentration N-type impurity introduction region 24, the inner surface of the capacitor formation groove 3 and the mask layer 13 are formed. A mask material layer 31 made of, for example, silicon nitride and extending continuously on the outer surface is formed by, for example, the CVD method (FIG. 4A).
.

Next, by etching the mask material layer 31, the region on the bottom surface of the capacitor formation groove 3 and the region on the top surface of the mask layer 13 of the mask material layer 31 are removed, and the mask material layer 31 is removed. A mask layer 32 that continuously extends only on the inner surface of the groove 3 and the inner surface of the window 21 of the mask layer 13 is formed (FIG. 4B).

In this case, the etching process for the mask material layer 31 is as follows:
It may be a reactive ion etching process known per se, for example, at a pressure l excited with a radio frequency of 0.3 W/cm2.
I believe this is a process using Qmtorr's CF4 gas ions and hydrogen ions.

Next, mask layers 13 and 3 are formed on the original silicon substrate 11.
2 as a mask, the mask layer 3
The area facing the window 33 of No. 1 and the mask layer 3 connected thereto
A high concentration N type impurity introduced region 34 similar to the high concentration N type impurity introduced region 22 described above in FIG. 22 is formed in the same manner (the fourth
Figure C).

Next, the mask layer 32 is removed using, for example, a phosphoric acid solution heated to a temperature of about 160° C. (FIG. 4D), and after or before that, the mask layer 13 is removed using, for example, a buffered hydrofluoric acid solution. 4E), thus, the capacitor formation groove 3 is formed from the main surface 2 side (S) from the original silicon substrate 11, and the capacitor formation groove 3 is formed from the open end side region 14 of the capacitor formation groove 3. A silicon substrate 1 is obtained in which the region 35 on the bottom side of the trench 3 is made into high-concentration N-type impurity introduced regions 24 and 34, respectively (FIG. 4E) 6 Next, as described above in FIG. 1G, a silicon substrate 1 is obtained. Next, by thermal oxidation treatment of the silicon substrate 1, a silicon oxide film 4 is formed which continuously extends on the main surface 2 side of the silicon substrate 1 and on the inner surface side of the capacitor forming groove 3 (FIG. 4F).

In this case, the silicon oxide film 4 is formed on the region 14 on the open end side of the capacitor forming groove 3 which is the high concentration N-type impurity introduction region 24 of the silicon substrate 1, and on the high concentration N-type impurity introduction region 34. On the region 35 on the bottom side of the capacitor formation trench 3, the regions 14 and 35 are high-concentration N-type impurity doped regions 24 and 34, respectively, so the formation speed is higher than on other regions. Therefore, the thickness of the silicon oxide film 4 is the same as that of the region 16 on the open end side region 14 of the capacitor forming trench 3 of the silicon substrate 1, the region 36 on the bottom region 35, and the other regions. It can be formed so that there is almost no difference or only a small difference between the region and the region.

Next, a conductive layer 5 is formed in a desired pattern on the silicon oxide film 4 in the same manner as described above with reference to FIG. 1H (FIG. 4G).

Including the above steps, a trench type MOS capacitor similar to the trench type MOS capacitor described above in FIG. 2 is manufactured.

The above is the first embodiment of the method for manufacturing a trench type MOS capacitor according to the second invention of the present application.

According to the first embodiment of the method for manufacturing a groove type MOS capacitor according to the second invention of the present application, the capacitor forming groove 3 is formed from the main surface 2 side, and the capacitor forming groove 3 is opened. A silicon substrate in which the region 14 on the end side and the region 35 on the bottom side of the capacitor forming trench 3 are made into high-11 N-type impurity-introduced regions 24 and 34, respectively, which are oxidized at a faster rate than other regions. 1 (FIG. 1 A-F to FIG. 4 A-F) and the oxidation treatment of the silicon substrate 1, a continuous layer is formed on the main surface 2 side of the silicon substrate 1 and on the inner surface side of the capacitor forming groove 3. Step of forming the extended silicon oxide film 4 as an insulating film (FIG. 4F)
It is possible to manufacture a trench type MOS capacitor similar to the trench type MOS capacitor described above in FIG. It has the characteristic of being able to

Furthermore, a groove-type MO according to the second invention of the present application shown in FIG.
According to the manufacturing method of the S capacitor, in the step of forming the silicon oxide film 4, the thickness of the silicon oxide film 4 is equal to that of the silicon substrate 1 even if the silicon oxide film 4 is not subjected to thermal oxidation treatment at high temperature. A region 16 above the region 14 on the open end side of the capacitor forming groove 3 and a region 36 above the region 35 on the bottom side.
and other areas, with little or no difference,
Can be easily formed.

Therefore, even if the silicon oxide film 4 is formed to have a small thickness in order to manufacture a trench type MOS capacitor with a large capacitance, the trench type MOS capacitor can be manufactured by using the conventional trench type MOS capacitor described above in FIG. It is not only compared to the trench type MOS capacitor obtained by the method for manufacturing a trench type MOS capacitor, but also compared to the trench type MOS capacitor obtained by the method for manufacturing the trench type MOS capacitor according to the first invention of the present application described above in FIG. It has the characteristics of being easily manufactured as having a high withstand voltage.

Embodiment 3 Next, a second embodiment of the method for manufacturing a trench type MOS capacitor according to the second invention of the present application will be described with reference to FIG.

In FIG. 5, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and a detailed description thereof will be omitted.

The method for manufacturing the trench type MOS capacitor according to the second invention of the present application shown in FIG.
A trench type MOS capacitor similar to that described above in the figures is manufactured.

That is, by performing the steps described above in FIGS. 1A to 1F and then performing the steps described above in FIGS. A capacitor forming groove 3 is formed using the mask layer 13 as a mask, and a region 14 on the open end side of the capacitor forming groove 3 in the original silicon substrate 11 is made into a high concentration N-type impurity introduction region 24, and a capacitor forming groove 3 is formed using the mask layer 13 as a mask. After obtaining a structure in which a mask layer 32 is continuously extended only on the inner surface of the mask layer 3 and the inner surface of the window 21 of the mask layer 13, the mask layers 13 and 32 are used as a mask for the original silicon substrate 11. By oxidation treatment, a mask material layer 41 made of silicon oxide is formed on the bottom side of the capacitor formation groove 3 of the original silicon substrate 11 to a thickness of, for example, 0.5 to 0.6 μm (FIG. 5A). This mask material layer 41 covers the mask layer 32 facing the window 33 of the mask layer 32 of the original silicon substrate 11.
It has a region that is relatively thin on the sides and relatively thick in the center, and a region that is connected to the region and extends below the mask layer 32 with a thickness that gradually becomes thinner.

In this case, the oxidation treatment for the original silicon substrate 11 is performed by heating the original silicon substrate 11 at 1000° C. in a combustion hydrogen atmosphere.
Thermal oxidation treatment may be performed at a temperature of 200 times.

Next, the mask layer 41 is etched by etching using, for example, a buffered hydrofluoric acid solution using the mask layer 32 as a mask.
The area under the mask layer 32 of the mask material layer 41 is removed, and the mask layer 32 of the original silicon substrate 11 is removed from the mask material layer 41.
forming a mask layer 42 in a region facing the window 33 (
Figure 5B). In this case, the mask layer 13 is also etched, thereby reducing its thickness.

Next, mask layers 13 and 3 are formed on the original silicon substrate 11.
2 as a mask, a high-concentration N-type impurity introduced region 34, such as phosphorus or arsenic, is formed in the original silicon substrate 11 in the mask layer 32, similar to the high-concentration N-type impurity introduced region 34 described above in FIG. 4C. The N-type impurity doped region 43 is formed in the same manner as the high-concentration N-type impurity doped region 34 (FIG. 5C).

Next, the mask layer 32 is removed using, for example, a phosphoric acid solution heated to a temperature of about 160° C., and then, before that, the mask layers 13 and 42 are removed using, for example, a buffered hydrofluoric acid solution.
In this way, from the original silicon substrate 11, the area 14 on the open end side of the capacitor forming groove 3 and the bottom part of the capacitor forming groove 3 are formed from the main surface 12 side. A silicon substrate 1 is obtained in which the side regions 44 are made into high concentration N-type impurity introduced regions 24 and 43, respectively (FIG. 5D).

Next, in the same manner as described above with reference to FIG. 4 (Fig. 5E).

In this case, the silicon oxide film 4 is formed on the region 14 on the open end side of the capacitor forming groove 3 which is the high concentration N type impurity introduced region 24 of the silicon substrate 1, and on the high concentration N type impurity introduced region 43. On the region 44 on the bottom side of the capacitor formation trench 3, which is formed as a capacitor, since these regions 14 and 44 are high-concentration N-type impurity doped regions 24 and 43, respectively, they are formed at a higher speed than on the other region. Therefore, the thickness of the silicon oxide film 4 is reduced to the area 14-F on the open end side of the capacitor forming groove 3 of the silicon substrate 1.
The region 16 and the region 36 on the bottom side region 35 are formed so that there is almost no difference, or even if there is, only a small difference between the region 36 on the bottom side region 35 and the region 36 on the bottom side. be able to.

Next, a conductive layer 5 is formed in a desired pattern on the silicon oxide film 4 in the same manner as described above in FIG.
Figure F).

Including the above steps, a trench type MOS capacitor similar to the IC trench type MOS capacitor described above with reference to FIG. 2 is manufactured.

The above is the groove type M○S capacitor according to the second invention of the present application! ! ! This is a second example of the if method.

According to the second embodiment of the method for manufacturing a groove-type MoS capacitor according to the second invention of the present application, the capacitor forming groove 3 is formed from the main surface 2 side, and the capacitor forming groove 3 is opened. The region 14 on the end side and the region 35 on the bottom side of the capacitor forming trench 3 are each heavily oxidized with N-type impurities introduced at a higher rate than the other regions.
Step of preparing a silicon substrate 1 (see Fig. 1A)
-F-・By oxidizing the silicon substrate 1 according to the steps shown in FIGS. 4A and B to 58th A to D, the silicon substrate 1 is
A step of forming a silicon oxide film 4 as an insulating film that continuously extends to the main surface 2 side of the 2nd side and the inner surface side of the 3rd surface for forming the passita (Fig. 5 [), and on the silicon oxide film 4. With a simple process including a step of forming a conductive layer 5,
A trench type M similar to the trench type MOS capacitor described above in FIG.
It has the feature of being able to manufacture OS capacitors.

Moreover, the groove-type MO according to the second invention of the present application shown in FIG.
According to the manufacturing method of the S capacitor, in the process of forming the silicon oxide film 4, the thickness of the silicon oxide film 4 can be reduced to that of the capacitor of the silicon substrate 1 without having to undergo thermal oxidation treatment at a high temperature. Region 14 on the open end side of the forming groove 3
It is easy to assume that there is little difference between the upper region 16 and the region 36 on the bottom side region 35 and other regions, or if there is, there is only a small difference. can be formed.

Therefore, even if the silicon oxide film 4 is formed to have a small thickness in order to manufacture a trench type MOS capacitor having a dog capacitance, the trench type MOS capacitor can be manufactured using the conventional trench type shown in FIG. Of course, compared to the trench type MOS capacitor obtained by the method for manufacturing a MOS capacitor, but also compared to the trench type MOS capacitor obtained by the method for manufacturing the trench type MOS capacitor according to the first invention of the present application described above in FIG. It has the characteristics of being easily manufactured as having a high withstand voltage.

[Brief explanation of the drawing]

Figure 1A~ shows a trench type MOS according to the first invention of the present application.
FIG. 3 is a line cross-sectional view of sequential steps showing an example of a method for manufacturing a capacitor. FIG. 2 is a cross-sectional view along the J'' line showing a trench MOS capacitor similar to the trench MO'S capacitor manufactured according to the present invention. FIGS. FIG.
FIG. 3 is a line cross-sectional view showing a first embodiment of a capacitor in sequential steps; Figure 5A~ shows a trench type MOS according to the second invention of the present application.
FIG. 7 is a line cross-sectional view of a second embodiment of a capacitor shown in step-by-step steps. 1・・・・・・・・・・・・・・・Silicon substrate ゛2
...... Main surface 3 of silicon substrate 1 ...... Capacitor formation groove 4 ...... ......Silicon oxide film 5
・・・・・・・・・・・・・・・Conductive layer 11...
・・・・・・・・ Original silicon substrate 12 ・・・・・
......Main surface 13 of original silicon substrate 11.
......Mask layer 14...
...... Region 16 on the open end side of the capacitor formation groove 3 of the silicon substrate 1 ...... Region 1 of the silicon oxide film 4 Region 24 on 14... High concentration N-type impurity introduced region 31... Mask material layer 32...・・・・・・・・・Mask layer 34・
・・・・・・・・・・・・High concentration N-type impurity introduction region 35 ・・・・・・・・・・・・・・・ Silicon substrate 1
Region 36 on the bottom side of the capacitor formation trench... Region 1i1 on the region 35 of the silicon oxide film 4 Figure 1 Figure 3 Figure 1 Figure 2 Figure 3 Figure 4 Whistle 4 Figure 4 Figure 5 Figure 5 Procedural amendment (method) Manabu Shiga, Director General of the Patent Office 1, Indication of the case Japanese Patent Application No. 117947/1982 2, Name of the invention Groove-type MOS Capacitor manufacturing method 3, relationship with the amended case Patent applicant address 1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo Name
(422) Nippon Telegraph and Telephone Public Corporation Representative Tsune Shinfuji 4th Director Address 5-7 Kojimachi, Chiyoda-ku, Tokyo 102
Hidekazu Kioicho TBR No. 820 No. 5, date of amendment order: September 25, 1980 (shipment date)
6. The number of inventions to be increased due to the amendment. Correct the phrase “No. , Figures 3 A-F.'' (3) Page 2, line 13 [Correct Figure 4 A-j to read Figure 4 A-GJ. (4) On page 16, line 16, "Figure 5 Δ~" has been corrected to Figure 5 A-FJ.

Claims (1)

[Claims] 1. A capacitor forming groove is formed from the main surface side, and at least a region on the open end side of the capacitor forming groove is oxidized at a higher rate than other regions. a step of preparing a silicon substrate into which a high concentration N-type impurity is introduced;
forming a silicon oxide film as an insulating film that continuously extends on the main surface side of the silicon substrate and on the inner surface side of the capacitor formation groove by oxidizing the silicon substrate; 1. A method for manufacturing a trench type MOS capacitor, the method comprising: forming a conductive layer. 2. In the method for manufacturing a trench type MOS capacitor according to claim 1, the step of preparing the silicon substrate includes forming a trench on the main surface of the original silicon substrate that will become the silicon substrate, corresponding to the trench for forming the capacitor. The highly concentrated N-type impurity is introduced into the original silicon substrate from the main surface side by forming a mask layer having a pattern of By forming a third high-concentration N-type impurity introduction region that will become the introduction region, and etching the original silicon substrate using the mask layer as a mask, the above-mentioned A method for manufacturing a trench type MOS capacitor, comprising the steps of forming a capacitor forming trench and forming the high concentration N type impurity doped region from the third high concentration N type impurity doped region. . 3. A capacitor forming groove is formed from the main surface side, and at least a region on the open end side of the capacitor forming groove and at least a region on the bottom side of the capacitor forming groove are formed, respectively. The first region is oxidized at a faster rate than other regions.
and preparing a silicon substrate to be used as a second high-concentration N-type impurity doping region, and oxidizing the silicon substrate to continuously extend it to the main surface side of the silicon substrate and to the only surface side of the capacitor formation groove. A method for manufacturing a trench type MOS capacitor, comprising: forming a silicon oxide film as an insulating film; and forming a conductive layer on the silicon oxide film. 4. In the method for manufacturing a trench type MOS capacitor as set forth in claim 3, the step of preparing the silicon substrate includes forming a trench on the main surface of the original silicon substrate that will become the silicon substrate, corresponding to the trench for forming the capacitor. and a process of introducing N-type impurities into the original silicon substrate using the mask layer as a mask. The step of forming a third highly concentrated N-type impurity doped region, which will become the N-type impurity doped region, and the etching treatment of the upper original silicon substrate using the above-mentioned mask layer as a mask are performed to form the third N-type impurity doped region in the upper original silicon substrate. forming the capacitor forming groove from the main surface side and forming the first high concentration N type impurity doped region from the third high concentration N type impurity doped region; After the step of forming the first high-concentration N-type impurity-introduced region, the N-type impurity is introduced into the original silicon substrate.
A method for manufacturing a trench type MOS transistor, comprising the step of forming the second high-concentration N-type impurity doped region in the original silicon substrate. □