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JPS60251443A - Backup device of programmable controller - Google Patents

Backup device of programmable controller

Info

Publication number
JPS60251443A
JPS60251443A JP59106501A JP10650184A JPS60251443A JP S60251443 A JPS60251443 A JP S60251443A JP 59106501 A JP59106501 A JP 59106501A JP 10650184 A JP10650184 A JP 10650184A JP S60251443 A JPS60251443 A JP S60251443A
Authority
JP
Japan
Prior art keywords
programmable controller
bus
regular
standby
backup
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59106501A
Other languages
Japanese (ja)
Inventor
Kenji Kakihara
柿原 健次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59106501A priority Critical patent/JPS60251443A/en
Publication of JPS60251443A publication Critical patent/JPS60251443A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Safety Devices In Control Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To improve the reliability of backup and to execute restoration easily by providing the titled device with two storage devices for storing and copying data on the way and a switching control circuit for detecting abnormality and switching a bus to the normal side. CONSTITUTION:Normally, changeover switches 54-56 are connected to the A side and a CPU1 in a working system is connected to an I/O 6 through a system bus 100 to control the I/O 6. When abnormality is generated in the working system, the changeover switch 54-56 are turned to the B side through the switching control circuit 52 under the condition that a trouble detecting signal 200 in the working system is activated and a trouble detecting signal 200 in a waiting system is inactive. Thus, the control is continued without stopping the system by using the data on the way at a normaly time. When the trouble is restored, backup operation is executed for the waiting system in control operation. If the abnormality is generated in the waiting system, the waiting system is automatically swiched to the working system to continue the control.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、常用系の異常時(二待機系(=バンプレス(
−切換えて制御を続行させるプログラマブルコントロー
ラのバックアップ装置(=関するものである。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a method for detecting abnormalities in the regular system (secondary standby system (=bumpless)).
- A backup device for a programmable controller that switches over and continues control.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来のプログラマブルコントローラのバックアップ装置
の一例を第4図(二示す。
An example of a conventional backup device for a programmable controller is shown in FIG.

第4図しおいて、CPU (中央演算処理装置)1およ
びPM (プログラム記憶装置)3は常用系のプログラ
マブルコントローラをCPU 2およびPM4は待機系
のプログラマブルコントローラを構成し、常時は常用系
が動作し、常用系の故障時はバス切換装置5)二よって
システムバスを切換えて待機系を動作させる。
In Figure 4, CPU (Central Processing Unit) 1 and PM (Program Storage Device) 3 constitute a programmable controller for the regular system, CPU 2 and PM4 constitute a programmable controller for the standby system, and the regular system is normally in operation. However, when the regular system fails, the bus switching device 5) switches the system bus and operates the standby system.

すなわち常時は、バス切換装顛5内の切換スイッチ54
.55.56がそれぞれA側(=あり、常用系のCPU
 1がバス100を介してIlo (入出力装置)6(
−結合され、PM3のプログラノ、(=従って制御動作
が行われると共(二、途中データはDM (データ記憶
装置)50(二保持され、さら(=DM 50 の途中
データは虜次待機系用のDM 51にコピーされる。
That is, at all times, the changeover switch 54 in the bus switching device 5
.. 55 and 56 are on the A side (= yes, regular CPU
1 via bus 100 to Ilo (input/output device) 6 (
- The program program of PM3 is combined, (=Therefore, the control operation is performed and (2), and the intermediate data is held in the DM (data storage device) 50 (2). is copied to the DM 51 of

52はバス切換diu御回路である。52 is a bus switching DIU control circuit.

この状態で常用系のCPU 1またはPM 3 に異常
が発生するとCPU 1から待機系のCPU 2への故
障検出信号200がアクティブ(二な9、CPU 2は
これを検出してバス切換制御回路52(ニバス101を
介して切換指令を出力し、切換スイッチ54,55.5
6をB側(二切換える。
If an abnormality occurs in the regular CPU 1 or PM 3 in this state, the failure detection signal 200 from the CPU 1 to the standby CPU 2 becomes active (second 9). (A switching command is output via the Nibus 101, and the changeover switches 54, 55.5
6 to B side (switch between two).

これ(二よって待機系のCPU 2がバス101を介し
てIlo 6 に接続され、DM 511ニコピーされ
ている正常な途中データを用いてPM4のプログラム(
二従い待機系で制御を継続する。
Therefore, the standby CPU 2 is connected to Ilo 6 via the bus 101, and the PM 4 program (
2. Control continues in the standby system.

これによってプログラマブルコントローラのバックアッ
プ動作が行われる。
This performs a backup operation of the programmable controller.

しかしながら上記従来のバックアップ装置は、常用系か
らの故障信号(二従って待機系側で行っておシ、待機系
(二切換9たあとはバックアップなしのシングルシステ
ムとして動作するので信頼性が低く、また常用系の故障
が回復して常用系(=戻し待機系でバックアップを構成
する場合は、待機系が正常(二制御動作している(二も
かかわらず、オペレータが手動で切換える必要があp、
切換操作が面倒になるという問題がある。
However, the above-mentioned conventional backup device has low reliability because it operates as a single system without backup after the failure signal (2) from the main system is switched, so the standby system operates as a single system without backup. When the failure of the regular system is recovered and the backup is configured with the regular system (= return standby system), the standby system is normally operating (2), but the operator must manually switch over.
There is a problem that the switching operation becomes troublesome.

〔発明の目的〕[Purpose of the invention]

本発明は、常用系と待機系とを対等な関係としてバック
アップの信頼性を高めると共(=、待機系から常用系へ
の復帰動作を容易にする合理的なプログラマブルコント
ローラのバックアップ装置を提供することを目的として
いる。
The present invention provides a rational programmable controller backup device that improves the reliability of backup by establishing an equal relationship between the regular system and the standby system, and facilitates the return operation from the standby system to the regular system. The purpose is to

〔発明の概要」 本発明は、常用系のプログラマブルコントローラが異ポ
(二なりたときシステムバスを待依系のプログラマブル
コントローラ(二切換えて制御動作をバンプレス(=継
続させるバス切換装置を備えたプログラマブルコントロ
ーラのバックアップ−aK+二おいて、それぞJt常用
系および待機系(−接続され制御動作側は途中データを
記憶すると共に非制御動作側は上記制御動作側の途中デ
ータのコピーを行なう2組のデータ記I’m装置と、制
御動作中の常用系または待機系の異常を検出してシステ
ムバスを健全側の系(二切換える切換制御回路を備え、
これ(二より常用系と待機系とを互(二対等(二バンク
アップ動作させて信頼性と操作性の向上をはかったもの
′Cある。
[Summary of the Invention] The present invention provides a bus switching device that switches the system bus between the standby programmable controller and the control operation bumplessly (= continues) when the regular programmable controller becomes abnormal. Backup of the programmable controller - aK + 2, respectively, are connected to the Jt regular system and standby system (-, the control operation side stores intermediate data, and the non-control operation side copies the intermediate data of the control operation side). Equipped with a data recording I'm device and a switching control circuit that detects an abnormality in the regular system or standby system during control operation and switches the system bus to the healthy system (two systems).
There is a system in which the regular system and the standby system are operated equally (two banks up) to improve reliability and operability.

〔発明の実施例〕[Embodiments of the invention]

本発明の一実施例を第1図1;示す。 An embodiment of the present invention is shown in FIG.

第1図では、従来の第4図(二おいてバス切換制御回路
52が待機系のCPU 2からバス101を介して制御
されていたの(二対して、常用系のCPU 1および待
機系のCPU 2の故障検出信号200および201(
−よって直接(二制御されておシ、他は第4図と同じで
ある。
In FIG. 1, the bus switching control circuit 52 is controlled from the standby system CPU 2 via the bus 101 (in contrast to the conventional system shown in FIG. Failure detection signals 200 and 201 of CPU 2 (
- Therefore, it is directly controlled (2), and the rest is the same as in Fig. 4.

すなわち第1図において、常時は切換スイッチ54、5
5.56がA側(二あυ、常用系のCPUIがバス10
0を介してIlo 6 に接続されて制御を行っている
That is, in FIG. 1, the changeover switches 54 and 5 are
5.56 is on the A side (2Aυ, the regular CPU is bus 10)
It is connected to Ilo 6 via 0 for control.

常用系(二異常が発生すると故障検出信号200がアク
ティブ(二なシ、待機系の故障検出信号201がインア
クティブであることを条件として切換制御回路52を介
して切換スイッチ54.55.56をB 1t11に切
換える。
When an abnormality occurs in the normal system (2), the failure detection signal 200 is activated (2) and the changeover switch 54, 55, 56 is activated via the switching control circuit 52 on the condition that the failure detection signal 201 in the standby system is inactive. B Switch to 1t11.

これ(二よって待機系のCPU 2はDM 51 T二
保持されている正常時の途中データを用いて、システム
を停止することなく制御を継続する。
Therefore, the standby CPU 2 uses the intermediate data during normal operation held in the DM 51 T2 to continue control without stopping the system.

この場合、常用系の故障が回復すると、制御動作中の待
機系(二対してバックアップ動作を行ない待機系に異常
が発生すると、自動的(=常用系(二切換って制御を継
続する。
In this case, when the failure of the regular system is recovered, a backup operation is performed for the standby system (2) that is in control operation, and when an abnormality occurs in the standby system, the system automatically switches to the regular system (2) and continues control.

従ってバックアップの信頼性が同上すると共(二、待機
系から常用系への彼帰動作が容易(二なる。
Therefore, the reliability of the backup is improved (2), and the return operation from the standby system to the regular system is easy (2).

次(二本発明の他の実施例を第2図(=示す。Another embodiment of the present invention is shown in FIG.

第2図は、第1図(=おけるDM50,51をそれぞれ
システムバス100 、1ot t=直接(=接続し、
バス切換装置5の内部(−DMAII71J御回路53
を設けてDM 50と51内の途中データを互−転送し
てコピーしてお9、他は第1図と同じである。
FIG. 2 shows that the DMs 50 and 51 in FIG.
Inside of the bus switching device 5 (-DMAII71J control circuit 53
9 is provided to mutually transfer and copy intermediate data in DMs 50 and 51, but the rest is the same as in FIG.

これ(=よって第1図と同じバンクアップ動作が行われ
る。また第3図は本発明のさら(=他の実施例を示すも
ので、この場合は複数の常用系(二対して1つの待機系
がバックアップ動作を行っている。
Therefore, the same bank-up operation as in FIG. 1 is performed. FIG. The system is performing backup operation.

例えばそれぞれCPUI、PM3およびCPU 11 
For example CPUI, PM3 and CPU 11 respectively
.

PM13より成る2組の常用系(二対して、CPU 2
 。
Two sets of regular systems consisting of PM13 (for two CPUs
.

PM4よシ成る1組の待機系が結合されておシ、各常用
系(一対してバス切換装置5,15が設けられ、異常(
二なった1組の常用系(二対して待機系(−よるバック
アップが行われる。
A set of standby systems consisting of PM4 is connected, and bus switching devices 5 and 15 are provided for each regular system (one pair) to detect abnormalities (
A backup is performed using the standby system (-) as opposed to the regular system (2).

バックアップの手順は上記第1図の場合と同様であシ、
これによって1組の待機系を用いて複数組の常用系(二
対するバンクアップが可能となる。
The backup procedure is the same as in Figure 1 above.
This makes it possible to bank up multiple sets of regular systems (two sets) using one set of standby systems.

〔発明の幼果〕[The young fruits of invention]

以上説明したよう(二本発明(二よれば、常用系と待機
系とが互(二対等(二バックアップ動作する信頼性が高
くて操作の容易なプログラマブルコントローラのバック
アップ装置が得られる。
As explained above, according to the present invention (2), a highly reliable and easy-to-operate backup device for a programmable controller in which the regular system and the standby system operate on an equal basis (2 backup operations) can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜弗3図は本発明の各実施例を示す回路図、第4
図は従来のバックアップ装置の一例を示す回路図である
。 1.2.11 中央演算処理装置(CPU )3.4,
13 プログラムi己・厖装置(PM)5.15 バス
切換装置 6.16 入出力装置(Ilo ) 50.51 データ記憶装置(DM )52 バス切換
制御回路 53 DMA制御回路 54、55.56 切換スイッチ 100.101 システムバス 200 、201 故障検出信号
Figures 1 to 3 are circuit diagrams showing each embodiment of the present invention, and Figure 4 is a circuit diagram showing each embodiment of the present invention.
The figure is a circuit diagram showing an example of a conventional backup device. 1.2.11 Central Processing Unit (CPU) 3.4,
13 Program management device (PM) 5.15 Bus switching device 6.16 Input/output device (Ilo) 50.51 Data storage device (DM) 52 Bus switching control circuit 53 DMA control circuit 54, 55.56 Changeover switch 100.101 System bus 200, 201 failure detection signal

Claims (4)

【特許請求の範囲】[Claims] (1) 常用系のプログラマブルコントローラが異常に
なったときシステムバスを待機系のプログラマブルコン
トローラに切換えて制御動作をバンプレス(=継続させ
るバス切換装置を備えたプログラマブルコントローラの
バックアップ装置(=おいて、それぞれ常用系および待
機系(二接続され制御動作側は途中データを記憶すると
共(二非制御動作側は上記制御動作側の途中データのコ
ピーを行なう2組のデータ記憶装置と、制御動作中の常
用系または待機系の異常を検出してシステムバスを健全
側の系(二切換える切換制御回昂を備えたことを特徴と
するプログラマブルコントローラのバックアップ装置。
(1) A backup device for a programmable controller equipped with a bus switching device that switches the system bus to a standby programmable controller to continue control operations bumplessly when the regular programmable controller becomes abnormal. A regular system and a standby system (two connected, the control operation side stores intermediate data, and the non-control operation side copies the intermediate data of the control operation side, and two sets of data storage devices are connected to each other. A backup device for a programmable controller characterized by having a switching control mechanism that detects an abnormality in a regular system or a standby system and switches the system bus to a healthy system (two systems).
(2)上記2組のデータば己憶装置をバス切換装置内(
二設け、上d己切換制御回踏の動作(二よってバスを切
換えるよう(ニした特許請求の範囲第1項記載のプログ
ラマブルコントローラのバックアップ装置。
(2) The above two sets of data are stored in the bus switching device (
2. A backup device for a programmable controller as claimed in claim 1, further comprising: (2) an operation of a self-switching control circuit (2) for switching buses;
(3)上記2組のデータ記憶装置をそれぞれ常用系およ
び待機系のバス(=接続すると共(二、上記バス切換装
置内にデータ記憶装置の途中データの転送を制御してデ
ータのコピーを行わせるDMA制御回路を設けた特許請
求の範囲第1項記載のプログラマブルコントローラのバ
ックアップ装置。
(3) The above two sets of data storage devices are connected to a regular bus and a standby bus, respectively (2) Data is copied by controlling the intermediate data transfer of the data storage devices within the bus switching device. 2. A backup device for a programmable controller according to claim 1, further comprising a DMA control circuit for controlling the programmable controller.
(4)複数の常用系(二対して1組の待機系を設け、そ
れぞれの常用系を共通の待機系でバックアップするよう
にした特許請求の範囲第1項記載のプログラマブルコン
トローラのバックアップ装置。
(4) A backup device for a programmable controller according to claim 1, wherein one set of standby systems is provided for each of the plurality of regular systems (two), and each of the regular systems is backed up by a common standby system.
JP59106501A 1984-05-28 1984-05-28 Backup device of programmable controller Pending JPS60251443A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59106501A JPS60251443A (en) 1984-05-28 1984-05-28 Backup device of programmable controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59106501A JPS60251443A (en) 1984-05-28 1984-05-28 Backup device of programmable controller

Publications (1)

Publication Number Publication Date
JPS60251443A true JPS60251443A (en) 1985-12-12

Family

ID=14435181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59106501A Pending JPS60251443A (en) 1984-05-28 1984-05-28 Backup device of programmable controller

Country Status (1)

Country Link
JP (1) JPS60251443A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63196901A (en) * 1987-02-10 1988-08-15 Mitsubishi Electric Corp Programmable controller restoration system for multiplexing system
JPH04354001A (en) * 1991-05-31 1992-12-08 Mitsubishi Electric Corp Redundancy controller

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55129850A (en) * 1979-03-28 1980-10-08 Hitachi Ltd Duplex system for multidata processor
JPS5692619A (en) * 1979-12-27 1981-07-27 Toshiba Corp Coupling method of electronic computer and direct memory access device
JPS5911455A (en) * 1982-02-18 1984-01-21 Mitsubishi Electric Corp Redundancy system of central operation processing unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55129850A (en) * 1979-03-28 1980-10-08 Hitachi Ltd Duplex system for multidata processor
JPS5692619A (en) * 1979-12-27 1981-07-27 Toshiba Corp Coupling method of electronic computer and direct memory access device
JPS5911455A (en) * 1982-02-18 1984-01-21 Mitsubishi Electric Corp Redundancy system of central operation processing unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63196901A (en) * 1987-02-10 1988-08-15 Mitsubishi Electric Corp Programmable controller restoration system for multiplexing system
JPH04354001A (en) * 1991-05-31 1992-12-08 Mitsubishi Electric Corp Redundancy controller

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