JPS60240294A - Digital pbx switch - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to private branch exchanges (PBXs) in the field of digital subscriber telephones, and more particularly to time slot buses and signals in digital PBX switches capable of carrying voice and data signals. Regarding buses.

~ l1 trivial 11 P and BX are increasingly used in today's telephone systems. A PBX system links telephones in an office, building, or factory together. Anyone in the PBX system can talk to anyone else in the system without the expense and time of using external lines and facilities.

PBX systems are becoming increasingly digital. - The caller's analog voice signal is converted into a digital representation. These digital signals are transmitted via a PBX system. Additionally, PBX systems are increasingly being used to transmit computer data signals. This is due in part to the availability of personal computers in homes and offices.

At the heart of this invention is the PBX switch shown in FIG. 1, which connects callers within the system and
If a call outside the PBX system is required, the caller is connected to an outside line, and the outside caller is connected to a line within the system. A PBX switch typically consists of multiple modules or “line cards.”
Each line card is coupled to a plurality of telephones or "terminals," and the line cards are connected to each other by a set of lines called a "bus," or often a "backbrane bus." Ru. 1st
A bus such as bus 10 in the figure includes a time slot bus. This time slot bus carries digital signals, for example voice or computer data.

In a digital PBX, the audio signal is sampled at a rate, typically 8,000 times per second (>8KHz), and the resulting voltage samples are sampled in a digital format, typically 8 kHz. The resulting sequence of bits (8,000 times 8, or 64 bits/sec) is converted into a pulse code modulated (PCM) encoding of the original audio signal. ＞It is called expression.Digital PBX is called PB
Conveys and switches PCM signals from one location to another within the X system. Finally, the PCM signal is converted back to an analog audio signal for human listening.

The PCM signal is transmitted on the bus 10.
The signal is conveyed during a particular time interval or time slot. Each time slot is a data PC
M64 can carry a stream of bits per second, so typically one time slot is required for each incoming or outgoing sound path. Of course, the timeslot is also 64. It can be used to convey computer data at speeds ranging up to 2 bits per second.

In addition to the time slot bus, the buff 10 has a signal bus. In addition to PCM-coded voice and data signals, digital PBX switches also accept ``signals''
i.e. 1l associated with each individual voice or data boat.
JI[l information must be conveyed and switched. For example, for rotary dial telephones, it is important to know whether the handset is "off the hook," whether digits have been dialed, etc. Therefore, a PBX switch collects signaling information from each individual voice port. , and there must be a way to convey it to a control device that acts on this information, for example by forming a voice connection.

All digital PBX switches must have some type of time slot bus and signal bus.

Many (conflicting purposes and problems exist) associated with these buses, among them: ('a) General Purpose Bus and Parallel Bus Routing.A bus in a typical system has several "positions." and each location has a bus connector that mates with a module or line card connector to connect the module to the bus.

A bus is "universal" if the same signals are present in the same position on every bus connector on the bus. In a generic bus, any module can be connected at any position on the bus. Advantages of such a system is obvious.

Fully parallel bus topology
) satisfies the requirements of a general-purpose bus. It can be easily designed with printed circuit board technology. Regardless of the number of locations on the bus, it can be easily connected at any point.

If you have a star topology (5tar) for the control unit,
topology), if a few lines are not parallel, there will be a different number of lines at each potential breakpoint and at each position that is 1,1 different from the rest.

(b) Maximum Data Transfer Bandwidth for Any Maximum Signal Rate Some performance characteristics of the bus are limited by the maximum switching signal rate on the bus. For example, faster switching speeds limit the maximum bus length and also
Produces more radio frequency interference. On the other hand, faster speeds allow the bus to convey more information with fewer wires.

Therefore, any maximum switching signal rate allows as many signals as possible to use this maximum rate to achieve maximum data transfer bandwidth.

<C> Free Time Slot Allocation Since different modules serve as different numbers of audio paths, the purpose of the general purpose bus is to provide centralized time slot switching (
Even when FIG. 2(a)) is used, it means that there should not be a fixed number of time slots associated with any arbitrary bus location. Rather,
Time slots should be assigned to individual modules as required by the particular system configuration.

(d> Addressability of individual modules Despite parallel bus wiring and versatility, some select individual line card modules for operations such as sending and receiving signal information, polling and resetting, etc. However, providing each module with a separate "module select" line would preclude the desired configuration of parallel bus wiring and the resulting versatility.

(e) Centralized or Distributed Time Slot Switching Two different time slot switching techniques are used in current PBXs. ``Centralized'' switching is shown in FIG. 2(a). In this approach, there are two logical time slot buses carrying voice and data signals. One bus carries outgoing time slot signals from the central control unit to the line card modules containing the individual port circuits, and the other carries incoming time slot signals in the opposite direction. Each bus has a dedicated time slot for every boat in the system. For example, voice port 11 X IT always provides its PCM signal on incoming timeslot X and receives the PCM signal on outgoing timeslot X.

Because the central controller receives all incoming timeslot signals and transmits voice or data signals on all outgoing timeslots toward the line cards, the timeslot switching circuitry in the central controller A connection can be made. For example, to connect boats
It is programmed to store M samples and at the same time store the PCM signals that arrive on the incoming timeslot Y and transmit them on the outgoing timeslot X.

In "distributed" switching, shown in Figure 2(b), there is logically only a single time slot bus and no centralized time slot switching circuit. Instead, each The line card module has a local timeslot switching circuit that allows signals coming from any port to be connected to any timeslot on the timeslot bus, and It can also listen to signals located inside and send them to any outgoing boat.

In this approach, in order to connect ports
and Q, but these time slots need not have a fixed relationship to X and Y. Thereafter, a local tie for boat X commands the bus slot switching circuit to transmit on timeslot P and receive on Q, while commanding Y to transmit on Q and receive on P.

Typically, the choice between centralized time slot switching or distributed time slot switching is based on the performance of the switching technology and the cost effectiveness of the technology available at the time of design. . For example, a distributed approach utilizes time slots more efficiently because time slots are not assigned to idle ports, whereas a centralized approach requires only one time slot switching circuit. Because of this, centralized approaches are typically cheaper.

The present invention accomplishes many of these objects and solves or substantially alleviates many of the problems discussed above.

1i211 The present invention provides a PBX switch with a plurality of modules, each module having at least one port for communicating signals to and from the PBX switch, and a port for communicating signals between the modules. determining the number of time slots coupled to the module to protect the plurality of parallel lines and signals on the communication line and activating the module to communicate during a predetermined portion of the time slots; clock means;
This allows more than one module to communicate in one time slot.

Thus, parallel communication lines provide a universal bus in this invention. Also, the data transfer rate is maximized without increasing the switching rate of the time slots.

Each module can be individually addressed.

Each module comprises means for generating a signal for identifying the module, and means for selecting a time slot for the module coupled to the identification means and the above-mentioned clock means, so that the time slot selection means is connected to the time slot selection means. A signal in a selected time slot on one of the coupled lines addresses the module.

The invention provides both centralized and distributed time slot switching. A PBX switch has a central control module in addition to line card modules with ports to the outside world. In centralized switching, a central control module transmits signals to the line card modules on a first set of parallel lines and receives signals from the line card modules on a second set of parallel lines. The control module also transmits and receives control messages to and from the module on a third set of parallel lines. For distributed switching, the control module disables the control module from transmitting signals on a first set of lines and a third set of lines in a predetermined time slot.
means for generating a control message indicating disabling of a control module on the assembly. The line card module itself is coupled to the third set of lines to transmit signals on the first or second set of lines and to transmit signals on the first or second set of lines during a predetermined time slot period. A means for receiving a signal is provided.

During these time slots, the PBX switch configuration operates in a distributed manner.

An understanding of the invention may be achieved by reading the following detailed description in conjunction with the drawings.

Preferred embodiments.

FIG. 1 shows the configuration of a typical digital PBX switch. This switch is typically located on central control module 1.
0 and a line card module 12Δ-D. Control module 10 includes individual modules 12A-D
Activates the core operations of the switch, such as collecting signal information from and coordinating operations between modules 12A-0. Line card modules 12A-D typically include:
It has multiple boats through which voice and data are communicated to and from the switch. Each of these boats had individual communication lines 13A-130 connected at the ends, such as telephones. Have a terminal. Other line card modules (such as 12D) may be connected to trunk lines 130, which are connected to other PBX switches (and other PBX systems) or to common telephone systems, etc. . Central control module 10 and line card module 12A
-D communicate via bus 10.

FIG. 3 shows details of a bus according to the invention that is particularly useful in digital PBX switches. This line is connected to the line card module via connectors 14Δ-14D. In accordance with the design goal of versatility, all pass lines are fully parallel, except for the unique module address terminal, which is selectively connected to ground line 41.

This will be discussed later.

The bus in Figure 3 is divided into three groups. 1st
The group is 11fA clock lines 21-23. The second group is a set of time slot lines 24
．． 25, through which voice PCM signals and data signals pass between modules of the PBX switch. Third
The group is a set of signal lines 26-29. These lines 26,29 carry signal information between modules.

Although all bus locations are the same except for the module address signals, different types of modules may be connected at each bus location. In particular, one module should be the "bus master" in the sense that it provides the clock and other mask control signals to which the other modules respond. In fact, this module is called the "central controller". One advantage of the invention is that the central control module (or any other module) may be connected at any bus location.

The first group of signals in FIG. 3 are clocks provided by the central control module on lines 21-23. FIG. 4 shows the timing of these clocks in this embodiment of the invention. Signal TCLKA on line 21 is clocked at 2.048 MHz, 33% duty cycle, and signal TCLKB on line 22 is similarly clocked at 2.048 MHz, 33% duty cycle, which is TCLKA
The phase difference is 1800. The importance of the shape (or duty cycle) of the clock signal in this invention will be discussed later. The period of any black 7ri is 1
/ (2,048MH2), or approximately 488
It is a nanosecond (ns).

The T' F RM signal is a framing signal that is activated only one clock period every 125 microseconds (μS), or once every 256 TCLKA or TCLKB periods. The interval between successive TFRM pulses is called a ``frame.'' This 12.5 microsecond period is standard for μ-low or eight-chip PCM.

An arbitrary maximum of 079 station wave numbers (in this example, 2.
048 MHz) the number of available time slots is maximized. In a conventional time slot bus design, a single time thrower 1-clock (“TCLK
”), the timeslot bus carries a single PCM or data signal for the entire TCLK period. 256 timeslots in 488 frames are defined.

The present invention uses two 2.048 MH2, 33% duty cycle differential drives, namely TCLKA and TCLKA, to divide two time slots into each 4
Defined within a clock period of 88 nanoseconds.

As shown in Figure 4, the time slots are divided into two groups: A'' and B11.
“A” time slot occurs when CLKA is high,
And when TCLKB is high, a "B" time slot occurs. Conventionally, in any group, the first time slot that occurs after the TFRM signal occurs is numbered 0, and the rest are numbered sequentially up to 225. Therefore, the TCLKA, TCLKB, and TFRM signals define 512 time slots, which are A-Q
to A-255 and B-0 to B-255.

Ja ya ++1+-bJ I, V r+ w I-r
) -s 7 During each timeslot interval of Mxe, audio PCM or data signals are carried in parallel on the timeslot bus on lines 24, 25. FIG. 3 shows a centralized time slot switching arrangement.

There are two time slot buses here, one of which is (
TSIN signal for the incoming time slot signal (from any module to the central control module), and TSOU, T for the outgoing time slot signal (from the central control module to any other module) on the other hand. It is for signals. Each of these buses is 8 bits wide. At any instant (time slot), the bus carries a complete 8-bit PCM or data signal.

In a centralized switching configuration, the central control module includes a time slot switching circuit that:
Store all of the signals received on the (incoming) TSIN bus 24 and store all of the signals received on the (outgoing)
) TSO, transmit on any time slot on the UT bus 5. Thus, the central control module can connect any incoming timeslot signal to any outgoing timeslot.

In a centralized switching configuration, the central control module always drives the TSOUT bus 25, but different line card modules drive the TSIN bus 24 during different time slots. Multiple power supply capabilities for driving the TSIN bus 24 can be achieved in a conventional manner using three-state drivers on each module. To drive the TS'IN bus 24,
The TSIN bus driver on a particular module is
It is activated only during the period when N time slots are assigned to that module, and disabled at all other times. Anyone who assigns -r, srN time slots to modules must 'ensure that each TSIN time slot is driven by λ by no more than one module.

Depending on how time slots are assigned to modules, consecutive TSI N time slots can be driven by different modules.

For example, referring to FIG. 4, time slot B-0
may be driven by module Q, while time slot A-1 is driven by module Q. In this case, it is important that the TSIN driver of module P is disabled before module Q is enabled.

Otherwise, both P and Q modules will be 1 for a short period of time.
7sIN bus and, depending on the driver's approach, will likely increase system noise and/or driver burden (and thus expect failure). Three-state transistor transistor logic (T
In the current dominant bus driver technology (TL), driver burden and system noise are particularly severe.

On the other hand, a three-state T (like the 74LS244 integrated circuit)
Manufacturers of TL drivers have attempted to minimize these effects by designing drivers to "turn-or" faster than "turn-on." Therefore, if one 74L8244 section on the bus is disabled and the other enabled at the same time, typically 15 seconds before the second section begins driving the bus, the first section will stop driving. On the other hand, it is not possible to disable one driver and enable the other at the same time. The difference in propagation delay in the activation logic for the two drivers and the physical distance between the drivers (which is important in bus systems) is a significant difference in the 1.55 nano-safety built into the 74L8244 part and similar drivers. Limits can be easily erased.

To eliminate these problems, the TCLKA and TCLKB clocks on lines 21 and 22 are set at 33%.
It has a duty cycle of Instead of being on for 50% of the 488 nanosecond period, the clock will be on for 1/3 of this period. This duty cycle allows TSIN and TSOU
There is a 16% duty cycle "dead time" between consecutive time slots on both T-buses 24,25.

In this embodiment of the invention, with a clock of 2.048 MH7, this is 8
A ``dead time'' of 1 nanosecond is reached.

Therefore, if more TCLK clocks are given to the system, the duty cycle time less than or equal to <1/N)T, where N is the number of clocks and is the period of the clock, will be Ensures that dead time is inserted between time slots.

This operating time is important in the DIN SIN bus 24 in a centralized switching configuration. Due to the clock configuration in this invention, the module simply clocks TCLK
A Also, there is a need to ensure that the TSOLIT path is driven only when TCLKB is high.
MHz, activation/
There is an 81 nanosecond margin available for the propagation delay of the logic on each module that makes the disabling decision.

In a centralized switching configuration, each module has a fixed set of time slots assigned to it during system execution. These timeslots are typically determined by hardware jumpers on the module or parameters loaded onto the module by a software initialization program.
When the system is configured (i.e. installed)
, assigned. The whole purpose of centralized (as opposed to distributed) switching is to minimize the size and cost of the circuitry on each line card module for allocating time slots.

The invention uses minimal circuitry for allocating time slots in the module. An important and innovative feature of the time slot allocation circuit is the two-stage time slot clock (CLKA and TCLKB).
). Time Slot Verse 24.25 (
TSIN and TSOUl-) each contain 512 time slots, but certain modules in centralized switching applications may
or T' CL K B and therefore 256 time slots (A group or B
(any of the groups).

This separation of Δ/B is important in practical terms, since 256 time slots are decoded with an 8-bit counter, while 512 time slots require a 9-bit counter. Since existing off-the-shelf counter circuits are 4-bit or 8-bit counters, this invention uses two 4-bit (or two 8-bit) counter packages to perform time slot decoding instead of three 4-bit (or two 8-bit) counter packages. Significant cost savings are realized by using only one (8-bit) counter package.

Another important contribution of this invention is that a minimal number of switches or programmable bits are used to allocate the set of time slots used by a particular module.

For example, if a module requires 8 time slots, then 2 of group A or B
The 56 time slots are divided into 32 sets of 8, with a 5-bit number assigning one particular set. On the other hand, if a module requires 64 time slots, then only 4 sets of 64 exist and a 2-bit number makes the allocation.

FIG. 5A shows an exemplary embodiment of time slot decoding circuitry in each line card module. This particular embodiment decodes time slots in either group Δ or group B, depending on the position of switch 38. The 256 time slots in the selected group are each divided into 16 sets of 16 time slots, with a particular set being assigned by a 4-bit number in switch 39. Time slots O through 15 are in phase O, time slots 16 through 31 are in set 1, and time slots 32 through 47 are in set 2.

The counter 31 is QA (lowest) or QH (highest)
is an 8-bit binary counter with an output of
It increments on every rising edge on the CLK input, except that the counter does not count when the LOAD input is at 1 on a CLK rising edge and instead loads the inputs represented by A through H.

The decoder 33 outputs its output (YO to Y15) at once.
It is a circuit that activates at most one of the following. If either ENl or EN2 is O, all outputs are zero. However, if ENl and EN2 are both 1, then the output corresponding to the binary value present at the inputs Δ to D will be 1, and the outputs of all other subelements will be O.

The TSIN bus driver 35 is a three-state driver whose output is disabled if the "enable" input is 0, and if the "enable" input is 1, then the input on AO or A7 The value is used to drive the TSIN bus 24.

The input register 36 has eight edge-triggered D-flips 70.
Contains whelk. If the ``CLK Activate'' input is 1 when a rising edge occurs on the CLK input, then the D input (TSOUT bus value) is stored in the flip-flop and transmitted to the line card module. In all other cases, the Q outputs will maintain their previous values.

Inverter 40 and AND gates 32,34 are standard logic gates. FIG. 5B shows a timing diagram for the decoding circuit of FIG. 5A. Clock Ding CL
KA is selected by switch 38 and switch 3
If the binary value at 9 is "o o o o°', then the circuit decodes the O set, time slots 0 through 15.T
On the falling edge of the clock TCLKA during the FRM pulse, a corresponding rising edge occurs at the CLK input of the counter 31, which causes the 1st clock 111100002 to be outputted to the counter outputs QH, QG, QF, QE, QD.

Load into QC, QB, and QA. The four "1" bits generate 1 at the output of the 4-power AND gate 31.Next, when the TC and LK'A clocks become 1, both ENl and EN2 of the decoder 33 become 1, Therefore, the 11 selected output (YO) also becomes 1,
Timeslot A on THIN and TSOtJT buses
Corresponds to -0.

For the next 15 TCLKA periods, QH to QE remain 1 and 1. On the other hand, Q via the remaining 15 binary values
D or QA count values are for time slots A-1 or A-1.
-15 decoder outputs Y1 through Y15 are enabled successively.

Next, suppose that instead of 0000, the binary value at switch 39 is 1110 (which is 1410). At this time, the initial value in the counter 31 will be 00010000 instead of 1 of 11110000. after that,
Started by TFRM pulse, counter goes to state “11”
110,000'' or the first state in which the decoder output (YO) is activated. Therefore, time slot set 14 (time slots 224 to 239) is decoded. This operation is similar for other groups.

AND goo 1 to 34 are “activation” of 3-state driver 35
input, so that it drives the TSIN bus 24 only during time slots in its assigned set and when TCLKA is 1, in accordance with the TSIN bus operating method described above. The "CLK ENABLE" input of register 36 controls register 36 so that its contents change in response to the time slots in the assigned set.

The output lines of decoder 33 and TSIN and TSOL
What is the module time slot bus for JT signals?
Conveys signals to and from internal circuits of a module. Although the internal circuitry of the module is not part of this invention, the invention is useful for providing line card modules and their internal circuitry.

Obviously, logically the same values can be used in any digital logic circuit. Inverter 4 in Figure 5
0 may be removed by redefining the polarity of switch 39 and discrete AND gate 32
is the “lip” already incorporated in the binary counter circuit 31.
ripple carry output".

Also, the TCLK clock selection and time slot set number need not come from switch 40. Other possibilities are, on the one hand, to ``hardwire'' these parameters according to the module's location on the bus, and on the other hand, by the microprocessor's output port bits located on the module and stored in latches. In the preferred embodiment, the TCL-K selection switch 38 includes: making them totally programmable.
is a function of the module's position on the bus, while the time slot-set selection switch 39 is programmable via the microprocessor on the module.

The overall configuration shown in Figure 5 is a power of 2, i.e. 2
” performs very well for any number of time slots. In such a case, only 8-n switches are used due to the number of time slot-tuples (switch 39 in FIG. 5). and 8-n input AND gate (
A gate 32) is used, while an n=2'y coder (decoder 33) is used. The starting time slot of this set is always a multiple of the number of time slots in the set.

For example, if you have eight sets of 32~ time slots,
-These are timeslots 0.32.64.96,12
8, 160, 192 and 224 and is executed for 32 consecutive time slots.

For those that are not powers of 2, the next highest power of 2 is "removed" to obtain a predetermined number of decoded timeslots. For example, for a 14-timeslot decryption, the 5A, except that the −Y15 and Y14 outputs of decoder 33 in FIG. , are not used internally by the module. The two remaining time slots are used by modules that only require two time slots.

In most configurations, including the preferred embodiment of the present invention, spreading the time slots used by the line card modules evenly across the entire 125 microsecond frame will combine them into one, as shown in FIG. 5B. Preferable than collecting. Expanding the time slot means that the local operation of the module is
Give more time to occur between ~, thereby reducing the cost and complexity of the module.

To widen the time slot, simply swap the A or D input with the H or H input, and swap the QA or QD input.
By swapping the specific power QE to QH, this is very easily accomplished in FIG. 5A. When this is done, the set O of time slots becomes time slot 0°16.32. -..., 240, and set 1 includes time slots 1.17.33.241, and so on.

In interpreting and reading the time slot assignments of Figures 5 and 5B, the internal module time slots in both the incoming and outgoing directions are exactly occur simultaneously. However, the signal generation and reception circuitry within the module is likely to be 1-timeslot (488 ns) or 1/2-timeslot offset (244 ns).
Request incoming and outgoing timeslots to occur at different times, with nanoseconds.

A 1-time slot offset can be obtained in almost any time slot decoding circuit using a knowledge flop or register delay at an appropriate point in the circuit. More difficult are 1/2-time slot offsets 1~. However, in this invention, the 1/2-evening basslot offset is 2
Step clock (TCLKA and TcLKB) 8
This is especially easy to obtain by e.g. In particular, referring to FIG. 5A, if T S I N driver 35 is enabled via AND gate 34 by clock T'CLKA, counter 31 and T S
OUT register 36 is clocked by four clocks TCLKB and vice versa.

The EN2 power of the decoder 33 is TCLKA, TCL according to the specific requirements for the decoder output in the module.
KB, or both clocks.

Therefore, each line card module
It has a certain number of switches 40 in the figure, or preferably has programmable bits in its timeslot decoding circuitry.

This number is the size of the set, ie. Corresponds to the number of time slots required to service the boats on that line card module. Furthermore, in addition to minimizing circuit size for allocating sets of time slots within a module, the present invention also sets a value or programmable bit in switch 40, so that even if different modules No matter how many time slots are requested, different sets of time slots may be designated 6 to different line card modules.

For example, assume that the following modules exist (for simplicity) all of which must use time slots in group B (i.e., group A is already filled).
Assignment Assignment blade... im slot #1 #2 P' 160-15 192-2070 64 64
-127 0-63 R16128-143208-223 864192-256,64-127 T 64? ? ? 12g-191 If the time slots are allocated sequentially and the set of time slots must start at a time slot whose set size is a multiple of 9, as already indicated.

Q, R, S and King will be assigned as shown in Assignment #1. Module T no longer has 64 valid consecutive time slots. however,
There are still 96 valid timeslots spread out over 256 groups.

Therefore, the invention makes the assignment of time slot sets on each module programmable, directly or indirectly, by the processor. In this embodiment of the invention, the set of time slots is directly programmable by the microprocessor on each line card module, and the central control module processor instructs the line card module microprocessor to
optimal timeslots by sending messages to them via a signal bus, which will be explained later with reference to the figure.
Have them assign groups.

The central module microprocessor allocates sets of time slots by designating the largest set first. The set with the next highest number of time slots is then designated. These steps continue until the smallest set is specified.

In this manner, the set of time slots is most efficiently allocated. Assignment #2 is one example. This type of programming for central module microprocessors is easily created by those skilled in the art.

FIG. 3 shows four module address connector lines for each module, MOD 3-. This indicates that 0 exists. These connectors are coupled to ground potential by ground lines 41 or left-side open in different patterns at each module location. Therefore, in theory there are 16 different "hard-wired 4-bit module addresses to identify each line card module. (Obviously, additional module address connectors can be used for larger numbers of modules. (It may be used to provide 5 lines for addresses, e.g. 32 addresses.) Each module with a different 4-bit address.

A typical method in the prior art to address modules by module is to provide a 4-bit module select bus on which the central control module provides the address of the selected module. Four comparators on each module connect the module selection bus to
Always has its own hard mapped address (MOD
3-0) to check whether it has been selected. A drawback of this prior art is the size of the module select bus, which is four lines for a 4-bit address, and even more lines if more than 16 module addresses are required.

The module selection bus in this invention includes one signal line 26. The MS signal on line 26 is 5
Up to 12 different modules can be addressed. In the preferred embodiment we describe, this MS
Line 26 addresses 32 different modules.

The TCLKA, TCLKB and TFRM clocks together define 512 unique time slots. For MS line 26, a smaller number of "selected slots"
is defined. The number of slots selected is the remainder obtained by dividing the number of time slots by 16. Therefore, every 16th of the 8-timeslots up to and including timeslots A-1, A-17, and 8-241 are also select-slots A,-1.

In this configuration, there are a total of 32 selection-slots, A-0 through A-15, and BL-0 through B-
It is numbered 15. 125 timeslots
While repeating every microsecond, the selection slots are fewer, so repeating every 8 microseconds.

In this invention, M during the corresponding selection-slot period
If the S signal is 1'', the module is selected, otherwise the module is not selected. MS line 26
By applying a suitable pattern above, the central control module can select none, only one, some of the line card modules, or all of the line card modules. It's okay. This is an improvement over the prior art in which only one line card module had parallel 4-bit buses that were selected without flexibility.

Figure 6A shows the selection logic on each module. Counter 42 is a 4-bit binary counter with output OA or QD that increments on each rising edge of the CLK input. However, if the LOAD input is 1 at the CLK edge,
Counter 42 will be loaded with the signal present at the Δ or D input terminals. D flip-flop 43 and inverters 44-46 are standard logic circuits.

FIG. 6B is a timing diagram of the circuit for explaining the operation of the circuit. Once every frame, counter 42
Loaded by the complement of the remossure address number obtained from the MOD3-0 connector. Connector 42 then increments on each rising clock 17 CLKA or TCLKB as selected by switch 47. For every 16th edge,
The counter 42 performs N transitions from the state ff11111 to the state MOOOO (the counter "state" is QD, QC, O
The value at the A output terminal). This transition is particularly important for QD
In the 1-0 conversion at the output terminal, the inverter 45
generates an O-1 transition on the output terminal of .

This in turn clocks the current value of the MS line 26 to the O flip-flop 43. This flip-flop output signal, MODSEL, indicates whether this module is selected or not. The MODSE signal is activated after 16 clock periods (about 8 microseconds) at the next 1111-0000i.
! Maintain a stable condition until the transition.

The selection-slot in which the 1111-0000 transition occurs is
Depends on module address number. For example, if the module address number of MOD 3-0 is 0010 and switch 47 selects CLKA, then the selected slot of interest is A-2. Therefore, the MS signal during selection-slot A-2 is:
Determine whether the module is selected for the next 8 microseconds.

Using both positions of switch 47, it is possible to select 32 different modules. In a preferred embodiment of this invention, ? Physical switch 47 is not used. Rather, half of the line card module
The counters 42 have their clock inputs connected to TCLKA, and half the counters have their inputs connected to TCLKB. This results in 32 module addresses rising, A-0 through A-15 and E3=O through B-15.

It should also be noted that there are some simplifications that do not change the spirit of the invention. In particular, inverter 44.4
5 is removed by simply flipping bits 0-2 of the hardwired module address number. Therefore, the preferred embodiment of this module selection circuit is:
It is constructed from an inexpensive 4-bit counter 42 and a D flip 70 tube 43, and is constructed at minimum cost.

There are many possible circuits for driving the MS line 26 by the central control module. FIG. 68 shows circuitry in the central control module that can be programmed to select none of the line card modules, or one or all of the line card modules. The counter 50 is
It is similar to counter 42 of FIG. 6A, except that it only counts when the input is one. The FFRM signal indicates that the signal occurs 16 times more often, i.e., during timeslot 1 as well as during timeslot 255.
It is a frame signal similar to TFRM, except that it occurs over 255 during periods 5, 31, and 47. This clock signal is TCLKA, TCLKB
It can be easily generated by an old FRM generating clock circuit.

In FIG. 7, these signals MODCEN, MODE
NA, MODENB and MOO, N3-0 are connected to a microprocessor 61 (FIG. 8) in the central control module that selects line card modules. Microprocessor 61 controls these signals as follows.

Set MODENA and MODENB@O to not select any module.

To select all modules, set MODENA and MODENB to 1, MODCEN to O, and MODN3-0 to 0QOO.

To select module A-i, set MODENA and MODCEN to 1 and select MODENB@0L-
and set MODN3-0 to a binary value representing i.

To select module B-i, set MODENB and MOD C, E N to 1, and set MODENA
is set to O, and MODN3-0 is set to a binary value representing i.

By using the above selection, only two more signal lines 27, 28 . A very efficient serial signal bus can thus be created using Ml (message in) and MO (message out). FIG. 10 shows the required circuitry on both the central control module and the line card module. The line card module circuit is repeated on all other line card modules. UART 60.70 are conventional general purpose asynchronous receiver transmitters that transmit and receive serial messages on their TXD (transmit data) output and RXD (receive data) input.

In many cases, LJART functionality is integrated on a single-chip microcomputer, such as the 8031 manufactured by Intel Corporation of Sunta Clara, California. The other elements in FIG. 8 are standard logic gates and components.

The configuration shown in FIG. 8 has several important advantages over conventional party line signal buses of the prior art. In the traditional party line signal bus,
The XD output from the centrally controlled LJART is directly bussed to the input of all other module UARTs, and the TXD output of all other module UARTs is connected to the MODS
EL gate 62.66 is the central control module u A
The benefit of driving the RxD input of RT, is to be directly ANDed. The undesirable consequences of such a configuration are as follows.

Whenever the central control transmits, all modules must take note and decide whether the message, the current message, is for them or not.

Some approach must be provided to prevent two or more modules from driving the Ml line 27 at the same time (otherwise their messages will be erroneous). Traditional techniques include polling, token passing, and collision detection.

A single failed module causes a “false” on the Ml line
By generating messages we can avoid signal buses for everything.

In this invention, the central control module can select the modules with which it wishes to communicate at any time. This is done using the module selection circuit described above. When any module is selected, its MO
DS, EL multiplied signal 1. Therefore, that T
The D IJ A R output is driven onto the Ml line 27 through the oven collector NAND gate 62 and the M
The signal on O line 28 is passed through OR gate 64 to its R
Coupled to the XD LIART input. If no module is selected, then NAND gate 62
The output is inactivated (floating) and RXD
The LJART input is forced to 1, which is a traditional UART
is in an “idle” state.

The ability of the central control module to select particular modules with which to communicate provides several advantages not available with traditional party line signal bus configurations.

Central Control - When a module is communicating with a particular module, other modules are undisturbed, i.e. their UARTs become "idle" RXD-like Mk:.

- The mechanism for selecting which module drives the MI line 27 is simple. Central control selects line card modules and performs 1. This module is the only module capable of driving the Ml line 27.

The central control module is protected from hardware and software failures on individual line card modules.
much more spared. Even if a module is "acting crazy" and continuously generates false messages on its UART's TXD output, the central control module simply refuses to select this module.

FIG. 8 shows how the microprocessor 71 on the line card module communicates with the microprocessor 61, such as a Motorola 68000 of Phoenix, AL, on the central control module. Each microprocessor 71 handles operations for its own line card module. The central microprocessor 71 handles operations for the entire PBX switch, including time slot assignment, which was previously discussed, and distributed time slot switching, which will be discussed later. Microprocessor 6.1.7
It should be understood that each of the 'l is also coupled to other parts of their module. The specific connections depend on the specific design of the module.

Another advantage of the invention is in the area of polling.

In a signaling system with a single master device (central control module) and multiple slave devices (other modules), the master device can contact the slave devices at any time, but the slave devices are It is possible to contact the main device only when you allow it.

Therefore, the master must have some means of discovering when the slave is about to send something. Two conventional methods are: : Polling. The master periodically sends a message to each slave, asking if it has anything to send.

Request to Send (RTS) line. Each slave device is 'RTS
It has its own logic signal called ``i'', where i is the number of the module, which is sent back to the master via the bus. When asserting this signal, the master periodically tests all RTS lines and initiates communication with the module that asserted RTS.

The polling method does not require additional hardware, but it does require processing overhead for sending and receiving slow (and usually ineffective) polling messages. The R'TS method is much faster and has less overhead (the dependent device is not hampered unless it actually has something to send), but it requires more hardware and Potentially RT
and a non-parallel bus to return the S line to the central control module.

In this invention, the RTS mechanism is achieved without extra hardware. To request a transmission, the line card module simply provides a continuous "O" logic value on the TXD output of its IJART and listens to the central control module, and this continuous O is a traditional UART. This is known as the "break" at -.

In a conventional party line system, one module sending successive breaks delays the M1 eran 27. However, in this invention, the central control module encounters a ``break'' only when it selects the module it is requesting.Therefore, the central control module takes ``break'' to mean a ``request to send.'' can be judged.

Upon detecting a "break", the central control module microprocessor 61 sends a message to the requesting module, asking it to send whatever it has or does not have to send. At this point, the requesting module is activated, removes the break, and
Roughly transmits the information on MI line 27.

Optionally, the central control module may ignore the "break" or simply force selected modules to receive the command. In any case, the module always removes the ``break'' during the period of communication with the central control module, and only after the conversation if it still has something further to send.
Send a pub break.

Another function of the signal bus of this invention is reset. In any digital system, it is necessary to reset the system to a known state upon power-up. Additionally, it is desirable to be able to reset the system in other cases, for example, if the system enters an unknown state during normal operation due to a transient error. For this reason, most systems include reset pushbuttons, watchdog timers, and other devices.

In a modular system with a microprocessor on each module, such as the one described here, it is possible for individual modules to enter an unknown state while the rest of the system functions normally. It is. In PBXs and other systems, resets usually cause an undesirable loss of service, so it is highly desirable to have a means to reset only the erroneous module without resetting other modules in the system.

In this invention, the module selection mechanism provides a novel means to selectively reset modules. As shown in FIGS. 3 and 8, a single "reset" signal is bussed on line 29 to all modules. The signals are driven by the output port bits of the microphone processor 61 in the central control module. On each line card module, this signal is routed by an AND) gate 65 to the local MODS
Combined with the EL signal to provide a local MOD reset signal.

In order to reset a particular module, the central control module then selects that module and asserts the ``reset'' signal.The central control module must carefully remove the ``reset'' signal before selecting the module and leaving 2. For example, the control module may select any other module with which the module wishes to communicate on the signal bus.Also, the central control module MS drive circuit shown in FIG. It is possible to select all modules so that all modules are reset at the same time to quickly and completely initialize the system.

Finally, the invention operates the time slot buses 24-25 in a distributed switching configuration.

In this respect, the time slot buses 24, 25 of FIG.
This has been described in the centralized switching configuration shown in FIG. 2A. The signal bus is particularly MJ line 27. M
The O line 28 and the MS line 26, with their associated circuitry, are controlled by the microprocessor 61 in a distributed switching configuration according to the present invention, so that the central control module can control the TSO during time slots.
It can be easily programmed not to drive U-cho path 25. Microprocessor 6 via MS line 26
1 selects a particular line card module and sends the microprocessor 71 on that card a time slot or time slot 2.1 on the TSOUT bus 25. Indicates that the slot is assigned to that line card module. Therefore, line card module 1. :t
, excluding TSIN bus 26, T S OUT bus 2
5 can be used to transmit PCM voice and data signals.

Microprocessor 61 also connects TSOLJT bus 25
Other time slots on the top can be assigned to other line card modules.

Similarly, microprocessor 61 allocates time slots on TSIN bus 24 for selected line quads to receive voice PCM and data signals. Therefore, go outside (the bus that carries the signal (TSoUcho bus 2)
5) and the bus carrying the incoming signal (TSIN bus 2)
4) Separation of the timeslot bus is removed. From the operation shown in FIG. 2A, a PBX switch with the present invention can also be made in the distributed switching configuration shown by FIG. 2B. Of course, the fifth
The TSIN bus 24 and TSIN bus 25 driver circuits of Figure A can be easily modified for bidirectional transmission and reception for distributed switching.

Although the foregoing description provides a complete and complete disclosure of the preferred embodiments of this invention, various modifications, other and similar constructions may be made without departing from the true spirit and scope of this invention. may also be used. Therefore, the above description and illustrations should not be considered as limiting the scope of the invention, which is defined by the appended claims.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a digital PBX switch. FIG. 2A shows a digital PBX operating in a centralized switching configuration, and FIG. 2B shows a digital PBX operating in a distributed switching configuration.
It is a figure showing BX. FIG. 3 is a diagram showing details of the time slot and signal bus of the present invention. FIG. 4 is a diagram illustrating clock operation and time slot timing of the present invention. FIG. 5A is a diagram illustrating a time slot decoding circuit used in a line card module connected to the time slot bus of FIG. 3, and FIG. 5B is a diagram illustrating the operating timing of this circuit. FIG. 6A is a diagram showing details of the module selection circuit on each line card module connected to the signal bus of FIG. 3, and FIG. 6B is a diagram showing the operation timing of this circuit. FIG. 7 is a diagram illustrating the central control module circuitry used to drive the line card module selection lines of the signal bus of FIG. FIG. 8 is a diagram illustrating central control module and line card module circuitry coupled to the message in, message out and reset lines of the signal bus of FIG. In the figure, 10 is a central control module, 12A, 12
8, 120, 12D are line card modules, 14A
, 14B, 14C, 14D are connectors, 21, 22.2
3 is the clock line, 24°25 is the timestamp line, 26, 27. ．． 28° 29 is a signal line, 30 is a synchronization line, 31 is an 8-bit counter, 33 is a decoder,
35 is a three-state driver, 36 is a register, 42.50 is a 4-bit counter, 60.70 is tJART, 61 is a central microprocessor 1, 66 is a module selection circuit,
71 indicates a line card microprocessor. Patent Applicant: DAVID Systems, Inc. Engraving of drawings (with major changes in content 1 FIG 2A. h-2EI. FIG, 3° FIG, - 4/a 7%, , l-1st time same B same field eup times same reason m field l
1111nmFIG, -5B. FIG, 8゜ Procedural amendment (method) % formula % 1. Display of the case Patent Application No. 239313 of 1982 2. Name of the invention Digital PB Coming Switch 3. Person making the amendment Relationship with the case Patent applicant address '701 East Yplin Avenue, Sunnyvale, California, United States
Name: D.A.V. 1' De, E Systems Inc. Representative: M. Erasam Bardawi 4, Agent Address: 2-3-9 Yachiyo, Tenjin, Kita-ku, Osaka 1 Building Telephone: Osaka (06) 351-6239 (Representative) Name: Patent Attorney (6474) Fukami Kube 6, Drawing plan subject to amendment 7, Contents of amendment: All drawings drawn in fruit production will be supplemented as shown in the attached sheet. Please note that there are no changes to the content. that's all

Claims (1)

Claims: (1) a plurality of modules each having at least one port for communicating signals, and a plurality of parallel lines coupled to the modules for communicating the signals between the modules; clock means for defining a plurality of time slots for the signals on the communication line and enabling the modules to communicate during predetermined portions of the time slots, thereby causing one or more modules to communicate. A digital PBX switch that communicates within one time slot. (2) The clock means includes a plurality of clocks,
Claim 1, wherein each clock operates at the same predetermined frequency and has a predetermined phase difference with the other of said clocks, and each of said modules is coupled to one of said clocks. Digital PBX switch described in section. (3) The digital PBX switch according to claim 2, wherein the number of clocks is 2, and the clocks operate with a phase difference of 1806. (4) The clock means includes a clock for generating signals with predetermined intervals to form a fixed number of said time slots within said intervals, and each module is configured to: means for allocating a set of time slots to the module, and means coupled to the allocating means and the clock means for generating a unique signal for each time slot allocated to the module; Thereby, in response to the unique signal, the module communicates with the assigned time slot.
BX switch. (5) The allocation means includes a set of switches, the number of switches indicates the number of sets of time slots within the frame signal interval, and the configuration of the switch includes a set of switches within the frame signal interval. 5. A digital PBX switch as claimed in claim 4, indicating a particular set. 6. The digital PBX switch of claim 5, wherein the set of switches takes the form of 1.1 sets of programmed bits. (a) said unique signal generating means is initialized at the beginning of each frame signal interval in response to said frame signal and one of said two clocks and counts in each time slot from said one clock; said counter generates an output signal indicative of said counted value; logic means coupled to said counter for generating a signal indicative of a logical combination of said counter output signals; and said output signal and said logic means; decoder means for responsively generating a signal on a unique line corresponding to the output signal, and wherein the logic means signal is a digital signal as claimed in claim 5, characterized in that the decoder means PBX switch. (8) the number of clocks is N, the period of the predetermined frequency is D, and the duty cycle of each clock is less than 1/N T or the nominal duty cycle of the clock; 3. The digital PBX switch of claim 2, wherein conflicting signals on said lines are thereby eliminated. (9) N is 2 and the duty cycle of each clock is 1/3 T. A digital PBX switch according to claim M8. (10) Each of the modules includes: means for generating a signal for identifying the module; and coupled to the identification means and the clock means. , means for selecting a time slot for the module, whereby the signal in the selected time slot on a first predetermined line of the thick lines coupled to the time slot selection means is The digital PE3X switch according to claim 1, characterized in that it is a module. (11) Each of the modules is further connected to the identification means and the first predetermined line so that the module has an address. 11. The digital PBX switch of claim 10, further comprising means for generating a module selection signal when the line is selected. input for transmitting signal data to a predetermined set of /
further comprising: output means; and means coupled to the module selection means and the input/output means for coupling the input/output means to the predetermined set of lines when the selection signal is present; Digital PB according to claim 11
X switch. (13) The input/output means includes a general purpose asynchronous receiver transmitter, and the predetermined set of lines includes a pair of lines, one line for communicating received signal data. 13. The digital PBX switch of claim 12, wherein the second line is for communicating transmitted signal data. (14) When said input/output means has signal data to be transmitted, said input/output means generates an output signal, said output signal being connected to said predetermined line when said selection signal is present. 13. A digital PBX switch according to claim 12, wherein the digital PBX switch is provided on a set of input/output means to indicate the status of said input/output means. (15) Each of the modules is connected to the identification means and a second predetermined line to reset the module based on a signal on the second predetermined line when the module is addressed. The digital P according to claim 10, further comprising means for
BX switch. (1,6> further comprising a central control module coupled to the parallel communication lines, the control module comprising:
transmitting signals to the module over a first set of parallel lines;
receiving signals from the module on a third set of parallel lines, the control module transmitting and receiving control signals to and from the module over the third set of parallel lines, the control module comprising: means for disabling itself from transmitting signals on the first set of lines in a time slot and generating a control signal indicating the disabling of the control module on the third set of lines; the module is coupled to the third set of lines and responsive to the control signal;
transmitting and receiving signals on the first set of lines;
The digital PBX switch of claim 1, further comprising means for receiving and transmitting signals on the second set of lines during the predetermined time slot. (17) a central control module and at least one line card module, the line card module having at least one port through which communication signals pass to and from the switch; The central control module and the line card module have a first set of lines for defining time slots and a second set of lines for conveying communication signals between the central control module and the line card module. and a third set of lines for conveying signaling information between the central control module and the line card module, the line card module comprising: the identification means and the line card module; and a first determined one of said three sets of lines, said digital PBX switch comprising means for selecting a time slot for said module. (18) In a digital PBX switch having a plurality of modules, each module has at least one port for communicating signals to and from the PBX switch, and for communicating the signals between the modules. a plurality of parallel lines of , a clock means coupled to said module for defining the number of time slots for said signal on said communication line, and a central control module coupled to said parallel communication means; The control module is connected to the first of the parallel lines.
transmitting signals to the module on the set of parallel lines, the control module receiving signals from the module on the second set of parallel lines, and the control module transmitting signals to the module on the third set of parallel lines. transmitting and receiving signals to and from the module at a predetermined time slot; means for generating a control signal indicating disabling of said control module on said set of lines, and said module is coupled to said third set of lines and responsive to said control signal to disable said control module on said first set of lines. and means for transmitting and receiving signals on a second set of lines during said predetermined time slots.