JPS60233737A - Incorporated test device of microprocessor - Google Patents

Abstract

PURPOSE:To improve the diagnosis capacity and to shorten the test time by setting the functions of a test function designating terminal to test a mapping array, a control memory and a microinstruction decoder independently of each other. CONSTITUTION:The functions of a mapping array 2, a control memory 3 and a microinstruction decoder 7 are tested independently of each other through a test function designating terminal 27 which supplies selectively the test function via a terminal outside a microprocessor. A control circuit 19 for test function 1, for example, delivers a decoding permission signal of an instruction register 1 to the array 2 and transfers the decoding output to be applied to an address register 4 to a test function register 11. While a decoding inhibition signal is delivered to the decoder 7 to actuate the function 1 only. Then a writing address is set at a data transfer address register 25, and a writing request signal is delivered to a bus transfer control circuit 8. This control action is repeated to test the decoding function of the array 2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprocessor using a microprogram control method.

(Conventional configuration and its problems) In recent years, as microprocessors have become larger and more sophisticated, the design and development of microprocessors has become more complex. Microprocessor test functions are becoming important in order to lower development costs and shorten development time.

A conventional microprocessor built-in test device will be described below. Figure 1 shows the configuration of a conventional microprocessor built-in test device. 3 is a control memory that stores a microprogram, 4 is a control memory address register that stores the read address of the control memory 3, and 5 is a mapping array 2.
6 is a microinstruction register that stores the microprogram that is the output of the control memory 3;
7 is a microinstruction decoder that decodes the contents of the microinstruction register 6; 8 is a bus transfer control circuit that controls bus transfer with the outside of the microprocessor; 26 is a test terminal that specifies test function operation; 9 is a test function control circuit; lO
1 is a sequencer that controls the operation timing of the test function control circuit; 11 is a test function output register that stores data to be output to the outside of the microprocessor during test function operation; and 12 is a data transfer address with the outside of the microprocessor used in test function operation. 13 is a segment base register that stores the transfer address segment, 14 is an adder that adds the contents of the test function address register 12 and the segment base register 13, and 15 is a bus transfer direction. This is a switching multiplexer.

In the above configuration, when the test function is activated from the test terminal 26, the test function control circuit 9 controls the gate circuit 5.
is invalidated, and a decoding prohibition signal is output to the microinstruction decoder 7. Further, the control memory address register 4 and the test function address register 12 are changed in sequence, respectively, and a write request signal is output to the bus transfer control circuit 8. As a result, the contents of the control memory 3 are sequentially read out to the outside.

However, with the above configuration, although it is possible to test the operation of the control memory address register 4, control memory 3, and microinstruction register 6, it is not possible to test the operation of other parts. Therefore, the operation of the entire microprocessor cannot be tested unless a test program using machine language instructions is created and executed completely independently of the read test of the control memory 3. In addition, testing using machine language instructions has the problem that when an error occurs, it is difficult to physically identify which part of the microprocessor is at fault.

(Object of the Invention) In view of the above problems, the present invention provides a mapping array for decoding machine language instructions, a control memory for outputting microinstructions,
The present invention provides a built-in test device for a microprocessor that can separately test the functionality of a microinstruction decoder that decodes microinstructions.

(Structure of the Invention) The present invention includes a test terminal that specifies the test function operation of a microprocessor, first, second, and third test function control circuits that separately control the execution of three types of test functions, and an execution two test function specification terminals for specifying test functions to be executed; a test function decoder for selecting the test function control circuit to be enabled from the contents of the two test function specification terminals; and a machine language instruction input from outside the microprocessor. an instruction register for storing the contents of the instruction register, a mapping array for decoding the contents of the instruction register, a control memory for storing the microprogram, a control memory address register for storing the read address of the control memory, and a mapping array for decoding the contents of the instruction register; a gate circuit that selects whether storage in the control memory address register is enabled or disabled; a microinstruction register that stores microinstructions; and one of the control memory output and data input from outside the microprocessor to the microinstruction register. The first output to
a selector for decoding the contents of the microinstruction register, a test function output register for storing the test function operation result, and one of the control memory address register and the microinstruction register for decoding the contents of the microinstruction register; This is a microprocessor built-in test device that is equipped with a second selector that selects and outputs a test function output register, and a test function address register that stores a data transfer address with the outside of the microprocessor during test function operation. By testing the functions of the mapping array, control memory, and microinstruction decoder separately by setting designated pins, it is possible to limit the test target for each test function, improve diagnostic ability, and reduce the time required for testing. It is something that can be done.

(Description of Embodiment) FIG. 2 shows the configuration of a built-in test device for a microprocessor in an embodiment of the present invention. In FIG. 2, l is an instruction register, 2 is a mapping array,
3 is control memory, 4 is control memory address register, 5
is a gate circuit, 6 is a microinstruction register, 7 is a microinstruction decoder, 8 is a bus transfer control circuit, 26 is a test terminal, IO is a sequencer, 11 is a test function output register, 13 is a segment base register, and 14 is an adder. 1 or more are the same as the configuration shown in FIG. 15 is a multiplexer that switches the transfer direction with the data bus outside the microprocessor; 16 is an instruction queue that stores the input machine language instruction string; and 17 is between the output of the control memory 3 and the data input from outside the microprocessor. 18 is a selector that outputs one of the output of control memory address register 4 and the output of microinstruction register 6, 19, 20, and 21 are control of test functions 1 and 2.3, respectively. circuit, 27 is a test function designation terminal for selecting and inputting a test function, 22 is a test function designation terminal 27
23 is an instruction fetch counter that stores the address of the instruction to be fetched, 24 is an instruction fetch control circuit, and 25 is data that stores bus transfer addresses other than instruction fetches. Transfer address register (used as test function address register when implementing test function),
A selector 28 outputs either the output of the instruction fetch counter 23 or the output of the data transfer address register 25.

Test function control circuits 19, 20, 21 in this embodiment
The control operation will be explained below.

FIG. 3 is a configuration diagram of the test function 1. In the figure,
All the constituent elements are the same as those in FIG. The test function 1 control circuit 19 outputs a decoding permission signal for the instruction register 1 to the mapping array 2 and transfers the decoding output to the control memory address register 4 to the test function output register 11.

A decoding prohibition signal is output to the microinstruction decoder 7, and only the test function 1 is operated. Furthermore, a write address is set in the data transfer address register 25,
A write request signal is output to the bus transfer control circuit 8. By repeating the above control operations, the decoding function of the mapping array 2 can be tested.

FIG. 4 is a block diagram of the test function 2, and all the constituent elements are the same as those in FIG. 2. The test function 2 control circuit 20 sets the control memory 3 to the control memory address register.
The output from the microinstruction register 6 is transferred to the test function output register 11. A decoding prohibition signal is output to the microinstruction decoder, and only the test function 2 is operated. Further, a write address is set in the data transfer address register 25, and a write request signal is output to the bus transfer control circuit 8. By repeating the above control operations, the contents of the control memory 3 can be tested.

FIG. 5 is a block diagram of the test function 3, and all the constituent elements are the same as those in FIG. 2. The test function 3 control circuit 21 sets the storage address of the microinstruction to be read in the data transfer address register 25 and outputs a read request signal to the bus transfer control circuit 8. The output of the selector 17 is made valid only during the period when a microinstruction is input, and is stored in the microinstruction register 6. During this period, a decoding prohibition signal is output to the microinstruction decoder 7. Next, the output of the selector 17 is invalidated and a decoding permission signal is output to the microinstruction decoder 7. By repeating the above control operations, microinstructions can be sequentially read and a functional test of the microinstruction decoder 7 and an operation test of the microinstruction execution unit can be performed.

According to this embodiment, the functions of the mapping array 2, the control memory 3, and the microinstruction decoder 7 can be tested separately by specifying the test function from a terminal external to the microprocessor.

The number of test items of mapping array 2 is a, control memory 3
If the number of test items in the microinstruction decoder 7 is b, and the number of test items in the microinstruction decoder 7 is C, then when testing the operation of the entire microprocessor using machine language instructions, the number of test items is a.
In contrast, with the configuration of this embodiment, the number of test items becomes a + b + c, and the time required for the test is significantly shortened.

Note that the test function designation terminal only needs to serve as an input terminal when the test function is activated, so it may be shared with other terminals. Also, there is no need to encode and specify test functions.

(Effects of the Invention) The present invention provides test function designation terminals on external terminals of the microprocessor, thereby testing the functions of the mapping array, control memory, and microinstruction decoder separately, thereby limiting the target of each test function. This method improves the ability to detect error locations, and also significantly reduces the time required to test the operation of the entire microprocessor, which has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional microprocessor built-in test device, FIG. 2 is a configuration diagram of a microprocessor built-in test device according to an embodiment of the present invention, and FIG. 3 is a configuration diagram of the test function 1. 4 is a block diagram of the test function 2, and FIG. 5 is a block diagram of the test function 3. ■...Instruction register, 2...Mapping array, 3...Control memory, 4...Control memory address register, 5...Gate circuit, 6.
...Micro instruction register, 7...Micro instruction decoder, 8...Bus transfer control circuit, 11...Test function output register, 15...Multiplexer, 1
7... First selector, 18... Second selector, 19
...Test function 1 control circuit, 20...Test function 2
Control circuit, 21...Test function 3 control circuit, 22...
・Decoder, 25...Data transfer address register (
test function address register), 26... test terminal, 27... test function designation terminal. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (4)

[Claims] (1) A test terminal that specifies the test function operation of the microprocessor, and a first and second terminal that separately controls the execution of three types of test functions.
．． a third test function control circuit; two test function designation terminals for specifying which of the three types of test functions is to be executed; and when the test function operation is specified by the test terminal, the two tests From the contents of the function designation terminal, the above-mentioned 1. Second. A test function decoder that exclusively selects and executes the third test function control circuit; and a bus transfer control circuit that controls bus transfer with the outside of the microprocessor. a multiplexer for switching the direction of data transfer; an instruction register for storing machine language instructions input from outside the microprocessor; a mapping array for decoding the contents of the instruction register; a control memory for storing a microprogram; a control memory address register that stores a memo read address; a gate circuit that selects whether or not the mapping array output is stored in the control memory address register; a microinstruction register that stores a microinstruction; and the control a first selector that outputs one of a memory output and a data input from outside the microprocessor to the microinstruction register; a microinstruction decoder that decodes the contents of the microinstruction register and outputs a control signal necessary for executing the microinstruction; and a second selector that selects and outputs one of the control memory address register and the microinstruction register. . a test function output register that stores the second selector output and outputs it to an external data bus via the multiplexer; and a test function address register that stores a data transfer address with the outside of the microprocessor used in test function operation. A built-in test device for a microprocessor, characterized by comprising: (2) A first test function control circuit outputs a decoding permission signal to the mapping array, outputs a control signal for enabling the gate circuit, and transmits the output of the second selector to the control memory address register. , a data transfer address is set in the test function address register, a write request signal is output to the bus transfer control circuit, and a decoding prohibition signal is output to the microinstruction decoder. A built-in test device for a microprocessor according to claim (1). (3) A second test function control circuit outputs a control signal that disables the gate circuit, sets a control memory read address in the control memory address register, and transfers the output of the first selector to the control memory. outputs a control signal that makes the second selector output the content of the microinstruction register, sets a data transfer address in the test function address register, and controls the bus transfer control circuit. 2. The microprocessor built-in test device according to claim 1, wherein a write request signal is output to the microinstruction decoder, and a decoding prohibition signal is output to the microinstruction decoder. (4) A third test function control circuit sets a data transfer address in the test function address register, outputs a read request signal to the bus transfer control circuit, and receives the first selector output from outside the microprocessor. A built-in test device for a microprocessor according to claim 1, wherein the microprocessor built-in test device outputs a control signal as a data input to the microinstruction decoder, and outputs a decoding permission signal to the microinstruction decoder.