JPS60224259A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve electrostatic breakdown strength in an output circuit side without deteriorating output characteristics, by providing a protecting circuit in which diodes and resistors are provided in parallel with a pair of transistors that constitutes an inverter at the final stage of the output circuit. CONSTITUTION:Between the source (VDD side) and the output node n1 of an N-channel type MOSFETQn, a resistor R2 in a P<+> type diffused layer, is connected in series so that the resistor R2 is located between a diode d2 and the source terminal of the MOSFETQn. The resistor is provided together with the diode d2, which is formed between a P type well region 2 and an N type diffused region 3b (a drain region of the MOSFETQn) as a parasitic form. Between the source (GND side) and the output anode n1 of a P-channel MOSFETQp, a substrate resistor R1 is connected in series so that the resistor R1 is located between a diode d1 and the source terminal of the MOSFETQp. The resistor is provided together with the diode d1, which is formed between a P type diffused layer 7b (a darin region of the MOSFETQp) and an N type semiconductor substrate 1 as a parasitic form.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor integrated circuit technology and further to electrostatic damage prevention technology, and relates to a technique that is effective for use as a countermeasure against electrostatic damage in output circuits in MO8 integrated circuits, for example.

[Background Art] In MO8 integrated circuits made of field-effect semiconductor elements, an abnormal voltage is applied to the external bottle due to static electricity, etc.
This may destroy internal elements.

Conventionally, 0MO8 type (complementary type) MO8 integrated circuit (hereinafter referred to as C
For example, a circuit as shown in FIG. 1 has been proposed as an electrostatic damage prevention circuit for an output circuit in a MOS-LSI. In other words, the output circuit (output buffer) in the 6MO8-LSI is
Channel type MO8FETQp and N channel type M O
It is composed of a CMOS inverter consisting of S F E T Q n.

Therefore, the PN junction diode d parasitic between the drain region (P-type diffusion layer) of the P-channel type MO8FETQP and the substrate, and the N-channel type MOSFET QP
As shown in FIG. 1, a parasitic PNN junction diode d between the drain region (N-type diffusion layer) of Qn and the P well region
(ground) and VDD. Therefore, when a positive abnormal voltage is applied to the output pad PO via the output bin, a current flows to the ground side through the diode d1. Also, vI and D are connected to the output pad PO.
When a negative abnormal voltage lower than d is applied, the diode d
2, current flows from the Vl)D side toward the output pad. This allows the MO8F that constitutes the output buffer to
Destruction of ETQp and Qn is prevented to some extent.

However, when an excessive current is passed through the diode dltd2 parasitic to the output buffer, the PN junction is destroyed and leakage occurs. Therefore, in order to prevent excessive current from flowing through the diodes d1+d2, which act as a protection, in the circuit shown in FIG.
This limits the current flowing through the diode dltd2 to the output pad PO.

However, in the above method, the on-resistance of the MO8FETs Qp and Qn that make up the output buffer is usually about Ω, so if the resistance value of the resistor inserted between the output buffer and the output pad is large, the output waveform Deterioration of the output characteristics, such as the sound becoming dull, occurs. In particular, this tendency becomes more pronounced as the on-resistance of the MO8FETs Qp and Qn forming the output buffer decreases. However, in order to improve the output characteristics, if the value of the resistor R is reduced, the diode dl
, d2 becomes weaker, and the PN junction of diode dlyd2 is more likely to be destroyed.

The inventor of the present invention has revealed that there are the above-mentioned problems.

Regarding the 0MO8 type, please refer to the r published by Electronics Digest Co., Ltd. on November 20, 1977.
MO5/LSI Design and Application” P.

67-P, 68 and P, 98-P, 100.

[Object of the Invention] An object of the present invention is to provide a technique that can improve the electrostatic breakdown strength on the output circuit side without deteriorating the output characteristics in an MO8 integrated circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, instead of inserting a resistor for overcurrent suppression connected between the output buffer circuit and the output pad between the protective diode and the output pad, it is inserted between these diodes and the power supply voltage terminal. This prevents the resistor for overcurrent suppression from being directly connected to the output node side when viewed from the output pad, and allows the resistor value for current suppression to be increased without deteriorating the output characteristics. This achieves the above-mentioned purpose of suppressing overcurrent and preventing electrostatic damage to elements constituting the output circuit due to abnormal voltage.

[Embodiment] FIG. 2 shows an embodiment in which the present invention is applied to prevent electrostatic damage in an output circuit in a 6MO8-LSI.

In this embodiment, a P-type well region 2 is provided by diffusion of P-type impurities in a portion of the main surface of a semiconductor substrate 1 made of N-type single crystal silicon where an N-channel type MO8FET is to be formed.

On the surface of this P-type well region 2, N-type diffusion layers 3a and 3b, which serve as the source and drain regions of the N-channel MO8FET, are formed in a self-aligned manner at appropriate intervals. A gate electrode 5a made of polysilicon or the like is formed on the channel portion between the N-type diffusion layers 3a and 3b via a gate insulating film 4a, thereby forming an output buffer on the P-type well region 2. An N-channel type MO8FETQn is formed for this purpose.

Further, on the main surface of the substrate around the P-type well region 2,
A relatively thick field oxide film 6 called LOGO8 is formed. On the main surface of the substrate 1 that is not covered with this oxide film 6, there is a P-channel type MO8FET.
P-type diffusion layers 7a and 7b, which become source and drain regions, are directly formed. A gate electrode 5b is formed on the channel portion between the P-type diffusion layers 7a and 7b via a gate insulating film 4b, thereby forming a P-channel MO8FET Qp for forming an output buffer.

Further, a bonding pad 8 made of an aluminum layer is formed on the field oxide film 6 near the MO8FET Qp or Qn.

Further, a P+ type diffusion layer 9 is formed from the surface of the P type well region 2 where the N channel type MO8FETQn is formed to the surface of the N− type substrate 1. On the other hand, the above P-channel type MO8FET on the main surface of the semiconductor substrate 1
An N1 diffusion layer 10 is formed at a position relatively distant from the QP, to which a wiring for applying a substrate potential is contacted.

The P-type diffusion layer 7a, which becomes the source region of the P-channel MO3FETQp, is connected to the ground potential GND of the circuit.
A power supply line that supplies a power supply voltage such as .

Furthermore, the P-type diffusion layer 7b, which becomes the drain region of MO8FETQp, and the N-type diffusion layer 3b, which becomes the drain region of MOSFETQn, are connected to a common bonding pad (output terminal) 8 by aluminum wiring. In addition, the gate electrodes 5a and 5b of MO8FETQp and Qn
Wiring is formed to input an output signal from an internal circuit (not shown). As a result, P-channel type MO8FETQp and N-channel type MO8FETQ
A CMOS inverter for an output valve is constructed of n.

Furthermore, in this embodiment, the circuit power supply voltage VD
The P-type well region 2 is connected to the power supply line that supplies D.
A potential is given to Further, the N++ scattering layer 10 formed on the main surface of the substrate 1 is connected to a power supply line that provides a ground potential GND of the circuit, so that the substrate 1 is biased to the ground voltage.

In the above embodiment, the P+ type diffusion layer 9 has an appropriate resistance value, and the N+ type diffusion layer 1 to which a substrate potential is applied
Drain region of 0P channel type MO8FETQP (P
The resistance of the substrate is interposed between the mold diffusion layer 7b).

Therefore, in the output buffer of the above embodiment, the third
As shown in the figure, a P-type well region 2 and an N-type diffusion layer 3b? The resistor R2 of the P+ type diffusion layer 9 is connected in series with the diode d2 parasitic between the drain region of the MO8FETQn and the drain region of the MO8FETQn, and the resistor R2 is connected between the diode d2 and the source terminal of the MO8FETQn. .

Part of the source of P-channel MO8FETQp (GN
A P-type diffusion layer 7b (
MO8FETQp drain region) and N-type semiconductor substrate 1
along with the diode d1 parasitic between the substrate resistance R
1 in series, and resistor R1 is diode d, and MO8
It is connected so as to be interposed between it and the source terminal of FETQP.

As a result, the resistors R1 and R2 connected in series with the diode dlyd2 are connected to the bonding pad (output pad) 8.
When an abnormal voltage is applied to the diode d1 or d2 and a current flows through the diode d1 or d2, the current is suppressed. This can prevent the PN junction between diodes d1 and d2 from being destroyed.

Moreover, according to the embodiment, the resistors R1 and R2 for suppressing the current flowing through the diodes d1 and d2 are not connected between the output pad PO and the output node n1 as shown in FIG. and MO8FET
It is connected between the source terminals of Qp and Qn. Therefore, for the output buffer (CMOS inverter), the current suppressing resistors R1 and R2 no longer serve as load resistances. As a result, even though resistors R1 and R2 are present,
There is no possibility that the change in the output signal of the output buffer becomes slow and the output characteristics are deteriorated.

FIG. 4 shows an example of the layout configuration of each element and wiring constituting the output circuit of the above embodiment.

In this embodiment, on both sides of the output bonding pad 8, the above-mentioned N
Source region (3a) and drain region (3b) of channel type MO8FETQn and P channel type MO8FE
A source region (7a) and a drain region (7b) of the TQp are formed parallel to the edge 11 of the semiconductor substrate 1. One ends of aluminum interconnections Q1 and J22 extending from pads 8 are in contact with drain regions 3b and 7b of each MOS FET Qn and Qp through contact holes 12, respectively.

On both sides of the rectangular P-type well region 2 in which the N-channel type MO8FETQn is formed, there are regions that partially overlap with the rectangular P-type well region 2 and extend toward the center of the substrate along a direction perpendicular to the edge 11 of the substrate. P+ type diffusion layers 9 serving as resistance R2 are formed in two rows. Power supply lines L1 supplying seven power supply voltages are connected to the ends of the pair of three medium-sized P diffusion layers 9 through contact holes 13, respectively.

In addition, a part of this power supply line L1 is an N-channel type M
It extends toward the O8FETQn, and its end is in contact with the source region (3a) via the contact hole 14. On the other hand, the source region (7a) of the P-channel type MO8FETQp is in contact with the power supply line L2 that supplies the ground potential GND through the contact hole 15.

Further, one end of a common signal line Q3 is connected to the gate electrodes 5a and 5b of the MO, 5FET Qn and Qp constituting the output sofa C:MOS inverter through a through hole 16, and is supplied from an internal circuit (not shown). An output signal corresponding to the output signal is applied.

The power supply lines L1+L2 and the signal line Q3 are formed of the same aluminum layer as the aluminum wiring Q1+Q2 and the bonding pad 8, although not particularly limited thereto.

According to the above embodiment, each output pad is The spacing between the pads, that is, the pitch of the pads can be narrowed.

In other words, when output transistors are placed on both sides of an output pad to realize a circuit as shown in FIG. Since the pads must be formed, the spacing between the pads becomes large. On the other hand, according to the layout configuration as in the above embodiment (FIG. 4), the diffusion layer 9 serving as a resistor is extended in a direction perpendicular to the edge 11 of the substrate, which has a relatively large margin. Therefore, even if a relatively long and narrow diffusion layer is formed to increase the resistance value, there is no need to widen the pad spacing.

Therefore, the layout method of this embodiment is suitable for configuring an output circuit of a semiconductor integrated circuit having a relatively large number of bins, such as a gate array, and exhibits excellent effects.

In addition, in the above embodiment, P constituting the current suppression resistor
The +-type diffusion layer 9 is divided into two parts and placed on both sides of the P-well region 2 and in parallel along the P-well region 2, as shown in FIG. P to surround the whole 2
A + type diffusion layer 9 may also be formed. In this way, the current flowing from the drain region (3b) of the MOS FET Qn, which is a noise source, toward the surrounding diffusion layer 9 is not concentrated in one part but is dispersed. Therefore,
This has the advantage that even if an abnormal voltage enters the output pad and a large current flows from the P-type well region 2 toward the drain region (3b), the PN junction is less likely to be destroyed.

Furthermore, since the drain region (3b) of MOSFETQn, which is a noise source, is completely surrounded by the P+ type diffusion layer 9, latch-up is less likely to occur.

Furthermore, in the above embodiment, the resistor R1 connected to the current suppressing diode d in FIG. An N-type well region is formed together with a P-type well region on the surface, and a P-channel type MO8FET is formed on the N-type well region. When using a process including the step of forming an N-type well region in this way, the output MOS FET Q
It is also possible to actively configure the resistor R1 by forming an N medium-sized diffusion layer from the surface of the N-type well region where p is formed to the main surface of the substrate.

[Effects] (-1) Instead of inserting the overcurrent suppression resistor connected between the output buffer circuit and the output pad between the protective diode and the output pad, connect these diodes to the power supply voltage terminal. I decided to interpose it between
When viewed from the output pad, the output characteristics change due to the effect that the resistor for overcurrent suppression is not directly connected to the output node side.

This has the effect of increasing the resistance value for current suppression without degrading the current, suppressing excessive current, and preventing electrostatic damage to the elements constituting the output circuit due to abnormal voltage.

(2) A pair of transistors constituting the final inverter of the output circuit are formed on both sides of the output pad connected to the output node, parallel to the edge of the semiconductor substrate, and diffusion constituting the resistor is formed. Since the layers are formed in a direction perpendicular to the edge of the semiconductor substrate, the spacing between the output pads can be narrowed, which has the effect of reducing the chip size.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the embodiment described above, the resistor R2 connected in series with the diode d2 is composed of a diffusion layer, but is not limited thereto, and can also be composed of a polysilicon resistor or the like.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the output circuit of a CMO8 integrated circuit, which is the field of application that formed the background of the invention. It can also be used in an output circuit of an MO8 integrated circuit having a push-pull type output stage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a protection circuit for preventing electrostatic damage in the output circuit of a CMO8 integrated circuit, and FIG. 2 is a circuit diagram showing an example in which the present invention is applied to the output circuit of a CMO3 integrated circuit. 3 is a circuit diagram showing an equivalent circuit of the embodiment, FIG. 4 is a plan view showing an example of the layout of the output circuit of the embodiment, and FIG. 5 is another layout. FIG. 2 is an explanatory plan view showing a configuration example. 1... Semiconductor substrate, 2... P-type well region. 3a...N-type diffusion layer (source region), 3b...
N-type diffusion layer (drain region), 4a, 4b... gate insulating film, 5a, 5b... gate electrode. 6...Field oxide film, 7a...P type diffusion layer (source region), 7b...P type diffusion layer (drain region) -8...Output pad (output bonding pad) ), 9...P medium diffusion layer (resistance), 10...
N10 diffusion layer, 11...edge, 12-15...
Contact hole, 16...Through hole, Qp.
...P channel type MO3FET. Qn...N-channel type MO3FET-R,. R2...Resistance for current suppression. Figure 5 // RoD

Claims (1)

[Claims] 1. In a semiconductor integrated circuit in which an output circuit is configured by field-effect transistors, a power supply voltage terminal and an output of the output circuit are connected in parallel to a pair of transistors that constitute an inverter at the final stage of the output circuit. A semiconductor integrated circuit device comprising a protection circuit having a diode and a resistor connected in series between a node and a protection circuit. 2. At least one of the pair of transistors constituting the output inverter is formed on a well region formed on the main surface of the semiconductor substrate, and a well region extends from the surface of the well region to the main surface of the substrate. A semiconductor layer of the same conductivity type is provided, and a predetermined potential is applied to the well region through this semiconductor layer, so that the resistor of the semiconductor layer is connected in series with the diode. The first claim characterized in that
The semiconductor integrated circuit device described in . 3. A pair of transistors constituting the output inverter are formed on both sides of an output pad connected to the output node so as to be lined up parallel to the edge of the semiconductor substrate, and a semiconductor layer constituting the resistor. 3. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is formed in a direction perpendicular to an edge of the semiconductor substrate.