JPS60214117A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To attain low power consumption by correcting a change of a control voltage to a VCO at PLL loop cut-off and executing intermittently the PLL operation in a PLL frequency synthesizer. CONSTITUTION:When a loop cut-off switch 311 is turned off by a control signal from a loop cut-off controller 314, the control voltage from a loop filter 310 is fed to an operational amplifier 312. The control voltage is changed when the switch 311 is turned off. Then an output of a ramp signal generator 313 is fed to the operational amplifier so as to correct the change in the control voltage and the result is fed as the control voltage to the VCO301. On the other hand, when the switch 311 is turned off, the power supply to a prescaler 304, a TCXO 308 and a PLL LSI 315 is stopped. The PLL operation is executed intermittently by the interruption of the power supply. Thus, low power consumption is attained.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to an ultra-high frequency multi-channel portable FM radio, and particularly to a frequency synthesizer used therein.
It is used to reduce the power consumption of radio equipment.

Conventional configuration and its problems Recently, 800-900 MEIZ band multi-channel mobile communication has been put into practical use, and efforts are being made to make it more portable.

To this end, the biggest challenge is to reduce the power consumption of radio equipment. The radio is multi-channel, equipped with a frequency synthesizer, and configures a highly stable local oscillator to select channels. However, since this frequency synthesizer is always operating even when the device is in standby mode, low power consumption of the synthesizer is an important issue in reducing power consumption during standby mode.

A conventional radio device and frequency synthesizer will be described using FIGS. 1 and 2.

FIG. 1 is a typical block diagram of an FM radio receiver, and the signal received by the antenna is transmitted to the reception signal terminal 101.
After being input to the RF amplifier 102 and amplified by the RF amplifier 102, the signal is input to the first mixer 103.

The first local oscillator 1 is connected to the other input terminal of the first mixer 103.
04 is connected, its output is the 11th F filter 1.
05 is input. Usually, a frequency synthesizer is used as the first local oscillator 104, and a communication channel is selected by specifying the frequency. The first F signal is input to the second mixer 106 and mixed with the output of the second local fixed oscillator 107, and the output is input to the IF filter 108, then the IF amplifier 109 and the amplitude limiting circuit 110, 7.
It passes through the M detector 111 and is FM demodulated. In the case of a car phone, etc., this receiving section performs simultaneous transmission and reception, so it is a part that is always in operation both during a call and during standby. The receiving section contains many circuits, but the power consumption is 60~
70 channels are occupied by a frequency synthesizer used for the first local oscillator 104.

Figure 2 shows a typical phase cycle (
Hereinafter, it will be abbreviated as PLL. ) is a block configuration diagram of a layered wavenumber synthesizer. Oscillation source is voltage controlled oscillator (VCO) 2
01, and this output is sent to the power divider 202 as a local oscillator output (
mixer input) and prescaler input. Prescaler 204 normally uses an ECL type swallow counter. After passing through the variable frequency divider 206, this output becomes one input of a phase comparator (hereinafter abbreviated as jD) 2o6. Also, a temperature compensated crystal oscillator (hereinafter abbreviated as TCXO).
The output of 207 passes through a fixed frequency divider 208 and is added to P and D 206 as a reference signal, and the phase is compared with the signal from the variable divider 205. After passing through a loop filter 209, the output is added to the VCO 201 as a control voltage. .

The variable division divider 206 can vary its frequency division number by a signal applied through the channel designation signal terminal 211, and the frequency division number is VC.

201 output frequency can be selected.

In such a configuration, 7oQ to 1oQ.

If we were to realize a MHz band synthesizer, at present it would require VCO201: 20mA, prescaler 2
04: 20-30mA, PLL LSI (
Broken line part 210) in Fig. 2: 5 mA, TCXO 207:
~5 mA, resulting in a total current consumption of 50 to 60 mA. That is, the signal source (VCO 201) also has the disadvantage that the frequency control system consumes more power.

Purpose of the Invention In view of the above-mentioned drawbacks, the present invention aims to reduce the average current consumption by operating a phase-periodic layer wave number synthesizer intermittently during standby of a wireless device, and to significantly reduce the average current consumption during stand-by. It is an object of the present invention to provide a frequency synthesizer that ensures sufficient frequency stability even when the frequency is not formed.

Structure of the Invention The present invention includes a first oscillator as an oscillation source, a prince scaler that divides the output of the first oscillator, and a first frequency divider that divides the output of the prince scaler according to a designated channel. a second oscillator as a reference signal source, a second frequency divider that divides the output of the second oscillator, and the first
．． a phase comparator that compares the output of the 20th frequency divider; a loop filter that integrates the output of the phase comparator; the output of the loop filter is input to one end, and the other end has a constant slope with respect to time. an operational amplifier, to which a voltage having a voltage of 1.0 is applied when the loop is cut, performs operational amplification to control the first oscillator; A power supply cutoff means for cutting off the power supply of the second frequency divider, phase comparator, or second oscillator, and a power supply cutoff means that performs recovery of the power cutoff performed by the power supply cutoff means when the loop is connected in accordance with a predetermined order. The above object can be achieved by providing a power supply return means.

Description of examples An embodiment of the present invention will be described below.

FIG. 3 shows a block configuration of a frequency synthesizer in an embodiment of the present invention.

In FIG. 3, the output of a voltage controlled oscillator (hereinafter abbreviated as VCO) 3o1 in a PLL frequency synthesizer used in radio equipment is distributed by a power divider 302, and one output is transmitted and transmitted through a local output terminal 303. Supplied to the receiver. The other output is frequency-divided by a prescaler 304 and input to a variable division divider 306. The variable frequency divider 305 has a number of divisions corresponding to a designated channel set by a synthesizer control signal 306 output from the radio control unit, divides the output of the prescaler 304, and uses phase comparators (hereinafter abbreviated as P and D). )3o7. On the other hand, the reference signal is a temperature compensated crystal oscillator (hereinafter abbreviated as TCXO).

) 308 is divided by a fixed frequency divider 309 to obtain P, D
This is the other input of 307. The outputs of P and D307 are passed through a loop filter 310 to remove noise etc., converted to direct current, and
This is the control voltage to C03o1. In order to perform the PLL operation intermittently to reduce power consumption, the above-mentioned V
It is necessary to constantly and stably supply the control voltage to the CO 301. For intermittent PLL operation, set loop disconnection switch 311 to P, D307 and loop filter 31.
0 or in series within a loop filter.

When this loop disconnection switch 311 is OFF (7), V
The CO301(7) control voltage changes as shown in FIG. Note that the slopes of a and b shown in FIG. 4 are determined by each intermittent operation type frequency synthesizer.
The main causes are considered to be leakage from the loop disconnection switch 311 and leakage from the control terminal of the VCO 301. In order to correct this change in control voltage, an operational amplifier 312 is provided between the loop filter 310 and the VCO 301. A fourth ramp signal generator 313 inputs a loop cutting signal to one end of the calculation width generator 312.
A signal having the same slope as the voltage slope shown in the figure is applied. Therefore, the control voltage applied to the VCO 301 can be kept constant. Furthermore, by using the operational amplifier 312 at the output of the loop filter 310, leakage of the charge held in the loop filter 310 is reduced, and control voltage changes can be reduced.

In addition, since the correction voltage is added using the operational amplifier 312,
Direct influence on the loop filter 310 can be reduced. Note that the loop disconnection switch 311 is controlled by a control signal from the radio controller, but the actual loop disconnection must be performed when there is no output from P and D307, so the output of the fixed frequency divider 309 and A loop disconnection signal is generated by the loop disconnection controller 314 under control from the radio control unit, and the loop disconnection switch 31
1. Control the ramp signal generator 313. In order to further reduce power consumption, after cutting the loop, the loop cutting controller 314 controls the grease scaler 304, TCX0308, and L for PLL.
SI315 (variable and fixed frequency divider 305.309, P
, including D307). Note that if the TOIO30B output is not stable due to intermittent power supply, the TCX0308 is not powered off. Such power supply enables stable intermittent PLL synthesizer operation with low power consumption.

Further, in the standby mode, the above intermittent operation is performed only when there is a constant reception level detected by the reception level detector 317 in the reception section 316 when receiving a channel, thereby enabling more stable PLL intermittent frequency synthesizer operation.

Other embodiments of the ramp signal generating means are shown in FIG. 6, FIG. 6, and FIG. 7, respectively.

The ramp signal generation circuit shown in FIG. 6 applies a voltage having a slope approximately proportional to the change in the control voltage of V C0301 to the operational amplifier, thereby correcting the change in the control voltage. The operational amplifier 501 inputs the output of the loop filter 310 with a DC component removed by a capacitor 502 (change in control voltage) via a resistor 503,
The in-loop arithmetic amplifier 50 is amplified by the intensification degree determined by
6 is input. The output from the loop filter 310 is input to the other end input terminal of the operational amplifier 506 via a resistor 507. As a result, the output voltage corrects the control voltage change, is amplified by the degree of increase determined by resistors 508 and 509, and is added to vCO3o1.

FIG. 6 shows a D/A converter 60 that generates a voltage with a slope determined by the specified channel value of a frequency synthesizer, and which receives a specified channel code signal 601 as input.
The output voltage of 2 controls the voltage variable resistor 603. The degree of amplification of the operational amplifier 604 is determined by the resistor 605 and the value of the voltage variable resistor. Resistor 606 and capacitor 6
07 generates a ramp signal with a constant slope, which is converted by an operational amplifier into a ramp wave having a slope corresponding to the designated channel. Switches 608 and 609 are driven by the loop disconnection signal, and switch 608 supplies power to an integrating circuit including ONL, resistor 606, and capacitor 607 when the loop is disconnected.

On the other hand, the switch 609 is turned on when the PLL loop is formed, discharging the charge in the capacitor 607, and setting the output of the ramp signal generation circuit to zero to eliminate any influence on the PLL loop. Note that the power supply connected to the resistor 606 may be of a constant potential.

In addition, the voltage variable resistor 6o3 may be the FET in the figure, or
Any material whose resistance value changes depending on the applied voltage may be used.

Further, the resistor 605 and the variable voltage resistor 603 may be replaced if the slope of the VCO control voltage is reversed due to an increase or decrease in the designated channel.

In FIG. 7, a voltage with a slope determined by the control voltage of the VCO 301 is generated, and one of the output signals (control voltage) of the loop filter 701 is passed through an operational amplifier 702 to V,
Added to C10301. The other voltage is input to the sample and hold circuit 703, which holds the vCO control voltage when the loop is disconnected by the loop disconnection signal. This operation makes it possible to generate a voltage whose slope is determined by the control voltage.

Note that the voltage generating circuit element 00 surrounded by the dashed-dotted line is the same as the configuration 600 shown by the dashed-dotted line in FIG. 6, so its explanation will be omitted.

By using the control voltage correction circuit as described above, stable intermittent operation of the frequency synthesizer is made possible.

Effects of the Invention As stated above, the present invention has the advantage that the standby of a wireless device is sometimes
L operation operating wave frequency synthesizer operates intermittently, greatly reducing average current consumption during standby, and PLL
Even when no loop is formed, sufficient frequency stability can be ensured, and the effect is significant.

[Brief explanation of the drawing]

Fig. 1 is a block wiring diagram of a conventional radio receiver, Fig. 2 is a block wiring diagram of a frequency synthesizer of the same main part, and Fig. 3 is a block wiring diagram of a frequency synthesizer of the same main part.
The figure is a block wiring diagram of a frequency synthesizer according to an embodiment of the present invention, Figure 4 is a characteristic diagram showing changes in vCO control voltage due to loop cutting, and Figures 6, 6, and 7 are diagrams of the frequency synthesizer in the same frequency synthesizer. FIG. 6 is a circuit diagram showing another embodiment of the ramp signal generating means. 301...VCO1302...Power divider, 303...Par°° local oscillator output terminal, 304...
...Prescaler, 306...Variable frequency divider, 3
07... Phase comparator, 30B... TOI
O1310...Loop filter, 306...
...Frequency synthesizer control signal, 311°°...
・Loop disconnection switch, 314...Loop disconnection controller, 315...PLL LSI, 316
. . . Receiving unit, 317 . . . Level detector, 312.501.506, 604. Finished02...
・Arithmetic amplifier, 503.607°・P°°co/de/su,
5o4゜605.507, 508.605.606...
...-Resistor, 6Q2...D/A converter, 603...Voltage variable resistor, 608.609
...Switch, 703...Sample and hold circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 N 48th! I ■Na darkness 1 no ac] (b Tomi O ro 7 Go Ching Ginsen) Figure 5 Figure 6 Figure 7

Claims (1)

[Scope of Claims] (1) A first oscillator as an oscillation source, a prince scaler that divides the output of the first oscillator, and a first scaler that divides the output of the prince scaler according to a designated channel. a frequency divider, a second oscillator as a reference signal source, and the second oscillator.
a second frequency divider that divides the output of the oscillator of the first oscillator;
a phase comparator that compares the output of the second splitter; a loop filter that integrates the output of the phase comparator; one end receives the output of the loop filter; the other end receives a constant slope with respect to time. an operational amplifier, to which a voltage having a voltage of 1.0 is applied when the loop is cut, performs operational amplification to control the first oscillator; a power supply cutoff means for cutting off the power supply of a second branch, a phase comparator, or a second oscillator; and a power supply return means for carrying out, in a predetermined order, the restoration of the power cut performed by the power supply cutoff means when the loop is connected. A frequency synthesizer comprising: (2) The frequency synthesizer according to claim 1, wherein the first oscillator is a voltage controlled oscillator and the second oscillator is a temperature compensated crystal oscillator. (3) The frequency synthesizer according to claim 1, wherein the first frequency divider is a variable frequency divider and the second frequency divider is a fixed frequency divider. (4) The frequency synthesizer according to claim 1, wherein a voltage having a slope substantially proportional to a change in the control voltage of the first oscillator is applied to the operational amplifier. (6) The frequency synthesizer according to claim 4, wherein a voltage having a slope determined by a channel designation value of the frequency synthesizer is applied to the operational amplifier. (6) The frequency synthesizer according to claim 4, wherein a voltage having a slope determined by the control voltage of the first oscillator is applied to the operational amplifier. (a) In the standby mode, the reception level at the time of reception is detected, and only when the level is above the specified level and a loop disconnection signal is received, the frequency synthesizer loop is disconnected.
2. The frequency synthesizer according to claim 1, wherein a voltage having a constant slope is applied to the operational amplifier.