JPS60189250A - Semiconductor device - Google Patents

Abstract

PURPOSE:To relieve the load of a metal wiring layer on a substrate, and to reduce the probability level of generation of trouble according to a step difference part by a method wherein a wiring pattern according to a semiconductor is formed in the semiconductor substrate using the semiinsulating semiconductor substrate. CONSTITUTION:Silicon ions are implanted on a semiinsulating GaAs substrate 21, and activating heat treatment is performed to form a wiring pattern 23. A nondoped I-type GaAs layer 24 is grown according to the organic metal thermal decomposition vapor phase growth method. Silicon ions are implanted to form the channel region 25 of an MESFET and a connecting region 26 to the wiring pattern 23. A gate electrode 28 is provided using a high melting point heat resistant material such as tungsten silicide, etc., and ion implantation and activating heat treatment are performed to form a source region 29 and a drain region 30. The necessary surface part is covered with an insulatingly protective film 31, and a drain electrode 32 and a wiring 33 are formed of metal wiring layers.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device 1w, and particularly to a semiconductor device 1t that includes a semiconductor wiring pattern in a base and can easily increase the degree of integration.

(b) Background of technology Microelectronics has become the foundation of modern industrial progress and has had a great impact on social life. Currently, the mainstay of microelectronics is silicon (Si) semiconductor devices ranging from transistors to ultra-large scale integrated circuit devices, and progress is being made in miniaturization of transistor elements to improve characteristics and increase the degree of integration. Miniaturization of transistor elements not only has the effect of increasing the number of integrated devices per unit area on a substrate, but also has the essential effect of improving transistor characteristics. In other words, for example, if the field effect of a transistor is reduced proportionally to 1/K, the impurity concentration eK times the impurity concentration, and the voltage 1 kl/K, then the propagation time and capacitance will be approximately 1/K, and the power consumption will be approximately It decreases to 1/ρ.

However, the electrical resistance of wiring and the like doubles due to the above-mentioned proportional reduction. Also, an increase in the scale of integration generally requires a higher factor increase in the scale of the interconnects. For these reasons, when expanding the scale of semiconductor integrated circuit devices, the wiring structure becomes an important issue that requires new means.

Furthermore, in order to improve operating speed beyond the limits based on the physical properties of silicon and reduce power consumption, we developed gallium arsenide (Ga), which has a much higher carrier mobility than silicon.
Semiconductor devices using compound semiconductors such as As) have been developed.

Among transistors using compound semiconductors, field-effect transistors (hereinafter referred to as FETs) have been developed first due to their simple manufacturing process, but with advances in the manufacturing process of compound semiconductor devices, Bipolar transistors are also being developed. Integrated circuit devices (hereinafter abbreviated as ICs) using these compound semiconductor transistors as elements generally have semi-insulating substrates to obtain effects such as a reduction in stray capacitance.

(C) Prior Art and Problems As an example of a conventional semiconductor IC structure, FIG. 1 shows a cross-sectional view of an 0MO8 structure. In the figure, 1 is an n-type semiconductor substrate, and a field oxide film 2 forms an n-type semiconductor substrate.
Channel and p-channel FET regions are defined, and the n-channel FET region has a p- type well layer 3, an n+
A p+ type source and drain region 4, a p+ type channel cut 5, and a p+ type source and drain region 6 and an n type channel cut 7 are formed in the region of the p channel FET, respectively. A gate electrode 9 is provided on the semiconductor substrate 1 via gate oxidation [8], and a first layer metal wiring 11 is provided on the gate electrode 9 and the source and drain regions 4 and 6 via the first layer interlayer insulating film 10. The metal wiring 1 of the second layer is connected to
3 is connected to the connection area 11A of the first layer metal wiring 11.

As shown in this example, most conventional ICs have a wiring structure that uses two metal wiring layers in addition to the gate electrode layer of the FET element, but the pattern density is already extremely large, and the transistor element However, the width of the wiring pattern and the like suppress the miniaturization, leaving no room for preventing an increase in resistance value.

To deal with this situation, various structures have been proposed, such as a structure with three or more metal wiring layers, and a structure in which the gate electrode layer of the FFI:T element takes on part of the role of the upper metal wiring. . However, for example, an increase in the number of metal wiring layers is accompanied by the problem of disconnection of the upper layer wiring or an increase in resistance value at the step part caused by the lower layer wiring, which is often a problem even in the conventional two-layer structure. The structure that uses this is advantageous in that the number of steps does not increase;
Scope of application is limited.

In the example described above, a metal layer is formed on a semiconductor substrate to perform wiring connection, but a structure in which a pattern of metal wiring or the like is embedded within the semiconductor substrate has also been proposed. This structure is often used due to the structural needs of semiconductor devices, and it coats a metal pattern to grow a semiconductor substrate and an epitaxial single crystal semiconductor, and also stabilizes it against temperature changes during the manufacturing process. Since it is extremely difficult to achieve this, it is impossible to use this type of structure for microscopic, highly integrated ICs, etc.

Furthermore, it is common practice to make electrical connections between semiconductor regions or between semiconductor regions and ohmic contact electrodes using low-resistance semiconductor layers or regions doped with impurities at a high concentration. In addition, in decoder circuits of semiconductor storage devices, etc.
There are examples in which high impurity concentration regions near the surface of a semiconductor substrate separated by a field insulating film are used as ground busbars and interconnection busbars.

However, the formation of connections by this semiconductor layer or region is
In current S L-ICs, etc., separation from other surrounding areas is complicated and it is difficult to miniaturize, so it is used with a high degree of freedom as a metal wiring layer on a semiconductor substrate as wiring between semiconductor elements. has not yet been reached.

(d) Purpose of the Invention In order to address the current situation described above, the present invention provides that a semiconductor wiring pattern is formed within a semiconductor substrate using a semi-insulating semiconductor substrate, and the surface of the semiconductor substrate is used for forming elements. It is an object of the present invention to provide a structure of a semiconductor device in which the metal wiring on the semiconductor substrate can have a margin, and the risk of the above-mentioned disconnection or the like is reduced. .

(e) Structure of the Invention A semiconductor device that achieves the above object of the present invention includes a semi-insulating semiconductor substrate, a buried wiring formed of a semiconductor containing impurities that is lattice matched to the substrate, and covering the buried wiring. The present invention is a semiconductor device in which a semiconductor base including an i-type semiconductor layer is provided with a semiconductor active element or a passive element selectively connected to the embedded wiring.

The semiconductor device includes a semiconductor device in which a wiring pattern is formed in or on a semi-insulating semiconductor substrate using a semiconductor that is lattice matched with the substrate and given conductivity by impurities, and the wiring pattern is coated on the substrate. In other words, a semiconductor layer that is usually non-doped and has a resistivity of about 1xlO [:Ω・m] or more is grown, and a semiconductor layer that is lattice matched to the substrate is grown, and the semiconductor layer is selected in or on the semiconductor layer according to the wiring pattern. This can be easily realized using a manufacturing method that includes a step of forming semiconductor active elements or passive elements that are connected to each other.

Methods for forming the wiring pattern in a semi-insulating substrate include a method of selectively implanting impurity ions and heat treatment for activation thereof, a method of selectively diffusing impurity ions, etc. Methods for forming a semiconductor layer on the substrate include epitaxially growing a semiconductor layer containing impurities and having a low resistivity on the substrate, and then masking the wiring pattern and etching away other parts to epitaxially grow a non-doped semiconductor layer; There is a method in which a non-doped semiconductor layer is epitaxially grown by implanting oxygen ions (0+) or the like into a portion other than the wiring pattern to increase the resistance. Alternatively, a manufacturing method may be implemented in which a semi-insulating substrate is selectively etched to form a groove-shaped wiring pattern, a low resistivity semiconductor is grown in the groove, and then a non-doped semiconductor is epitaxially grown on the entire surface.

(f) Embodiments of the Invention The present invention will be specifically described below by way of embodiments with reference to the drawings. In addition, as an example, a semi-insulating GaAs substrate is used to fabricate a parallel type F'ET (hereinafter MESF'E).
Let us take I (1), whose element is I (abbreviated as T).

FIGS. 2(a) to 2(e) are step-by-step sectional views showing the first embodiment of the present invention.

FIG. 2(a) A resist H4 is formed on a semi-insulating GaAs substrate 21 having a reference resistivity of, for example, about I.times.107 (Q-m), and a mask 22 is formed by opening an intended wiring pattern.

Next, a donor impurity such as silicon (St) is dosed at a dose of 2×10” at an energy of about 170 (Key).
Ion implantation is performed to the extent of (a;i2:].The mask 22 is removed and the N
! The substrate 21 is coated with lσ (not shown) and subjected to activation heat treatment for about 10 minutes at a temperature of, for example, aso o C'c], and the wiring pattern 23 is coated with an impurity of 8 x 10''(cm-'). 3. Resistivity 3 X I Q
It is formed to about 3 [Ω・σ].

Refer to FIG. 2(b) After removing the protective film and removing the damaged layer on the surface of the substrate 21 by contacting with, for example, hydrogen chloride (HCA) gas, in this embodiment, the organic metal pyrolysis gas phase Growth method (
Trimethylgallium (Ga(CH3)3) and hyflucin A were obtained using the M, O'C'VI method).
Using SH3 as a raw material gas, non-doped l-type Ga, A
The S layer 24 is grown on the substrate 21 to a thickness of, for example, about 0.9 [μm].

Note that a semiconductor layer doped with impurities may be grown to form a semiconductor active element, etc., but in this case, a type 1 non-doped layer with a thickness of approximately 0.5 [μm] or more is grown between the wiring pattern 23 and the wiring pattern 23. interpose a double layer.

Refer to FIG. 2(c) MES FET channel region 25 and wiring pattern 2
A connection region 26 with 3 is formed. Ion implantation into the channel region 25 of this embodiment is performed using conventional techniques such as silicon (Sl).
) at an energy of about 601:KeV).
The ion implantation into the connection region 26 was performed using silicon (Silr energy of about 500 (Key))"-base 84 x 10".
crn-2].

After the ion implantation, the mask 27 is removed, a protective film made of AIN or the like is provided, and heat treatment is performed at a temperature of 80° C. for about 10 minutes. As a result, the maximum impurity concentration in the connection region 26 is approximately 6×10” [c+++”:].

Referring to FIG. 2(d), for example, tungsten silicide (WS) is
A gate electrode 28 is provided using a high-melting-point heat-resistant material such as i), and ion implantation and activation heat treatment are performed to form a v source region 29 and a drain region 30 by a self-alignment method.

It is covered with an insulating protective film 31, and ohmic connection electrodes, in this embodiment, a drain electrode 32, wiring 33, etc. are formed in the first metal wiring layer. Furthermore, the second
It is possible to provide layered metal wiring in the conventional manner.

Next, FIGS. 3(a) to 3(C) are process-order sectional views showing a second embodiment of the present invention.

See FIG. 3(&) Semi-insulating GILA8 substrate 41 similar to the first embodiment
An n+ type QaAs layer 42 is formed thereon to a thickness of, for example, 0.2 to 0.
It grows epitaxially to about 5 [μm].

In this example, silane (81H4) was used as a cine purity source by MOCVD method, and the impurity concentration was set to IX 1020.
[:crn-3], resistivity 2X10-4 [Ω
m] degree.

A wiring pattern mask 43 is provided on the n+ type GaAs@ 42 by phosphorography and selective etching is performed to form a wiring pattern using the n+ type GaAs 1@42 (see FIG. 3).

Refer to FIG. 3(e).N+ type QaAs layer 42, which is the wiring pattern described above, is rationally embedded in a non-doped GaAs FF444 film to a thickness of 0.5[deg.] above the wiring pattern by MOCVD, for example.
micrometer].

As described above, a semiconductor substrate in which a wiring pattern is embedded is obtained. This is equivalent to the state shown in FIG. 2(b) of the first embodiment, and the semiconductor device can be completed by the same manufacturing method as in the above example, but the wiring pattern is formed by an epitaxial growth layer. Second, its resistivity is reduced.

Further, FIGS. 4(a) to 4(e) are sectional views showing the third embodiment in the order of steps.

Referring to FIG. 4(a), on a semi-insulating QaAa substrate 51 similar to those in each of the above embodiments,
Silicon dioxide (SiOz), Silicon elide (
A mask 52 having an opening for a wiring pattern is provided using Si3N4) or AljN. The substrate 51 is selectively etched to form a wiring pattern 53f in the form of a groove.

Refer to FIG. 4(b).N+ type QaAs similar to that of the second embodiment is grown. Due to this growth, the inside of the trench of the wiring pattern 53 is of n+ type Qa.
The As single crystal grows and stops growing when it reaches the same height as the surface of the substrate 510. Further, amorphous to polycrystalline GaA 354 is deposited on the mask 52.

A QaAs layer 54 and mask 52 are then deposited on the mask.
and remove. During this removal, it is desirable to protect the surface of the wiring pattern 53 made of single-crystal GaAa with a resist film, but in this patterning, it is recommended to use the exposure mask used in the phosphorography method to form the mask 52 first. can.

Note that this removal can be carried out using, for example, hydrofluoric acid (HF):nitric acid (HNO).
3) It can be carried out using a mixed solution of 5:1 (volume ratio).

Referring to FIG. 4(0), a non-doped GILAB layer 55 is grown over the entire surface of the substrate 51 in the same manner as in the 55th embodiment. The subsequent steps are the same as in the previous embodiment.

+1 As in the above-described embodiments, there are various manufacturing methods for the semiconductor wiring pattern of the present invention, and it is possible to select the optimum method and easily adapt it to other manufacturing processes.

In the above embodiment, a GaAs MES FET is targeted, but other materials other than GaAs, such as indium phosphorus (InP)
) type semiconductor materials, or MIS type FETs, etc.
The present invention can also be applied to ICs including semiconductor active elements such as bipolar transistors, and passive elements such as capacitances and resistors.

Further, in the above embodiment, the wiring pattern is formed in a single layer, but if necessary, the wiring pattern can be formed in two or more layers by a similar manufacturing method.

(g) As described in detail, according to the present invention, at least a part of the inter-element wiring of an integrated circuit device is buried in the semiconductor substrate and the surface of the semiconductor substrate is flat. The burden on the metal wiring layer on the semiconductor substrate is alleviated, and the risk of failure due to differences in level is reduced. Further, the area used for forming elements on the surface of the semiconductor substrate is not reduced. Therefore, it becomes possible to further increase the degree of integration of the integrated circuit device.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an example of conventional wiring of a semiconductor integrated circuit device, FIGS. 2(a) to (e), and FIGS. 3(&) to (e).
) and FIGS. 4(a) to 4(c) are sectional views showing embodiments of the present invention, respectively. In the figure, 21.41 and 51 are semi-insulating Q aA
8 substrate, 23.42 and 53 are wiring patterns according to the present invention, 24.44 and 55 are i-type GaA three layers, 25 is a channel region, 26 is a connection region, 28 is a gate electrode, 29 is a source region, and 30 is a drain region , 31 is an insulating protective film,
32 is a drain electrode, and 33 is a wiring. Dormitory number 3? Shouting fist 2 Kumine 3 Shouting ((21 committee 4 song ((b

Claims (1)

[Claims] A semiconductor substrate including a semi-insulating semiconductor substrate, a buried wiring formed of a semiconductor containing an impurity that is lattice matched to the substrate, and an i-type semiconductor layer covering the buried wiring,
1. A semiconductor device comprising semiconductor active devices or passive elements selectively connected by embedded wiring.