JPS60160645A - Laminated semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a through-hole construction which can expect a stable and high process yield by making a construction wherein a through-hole is provided in a semiconductor substrate, the aperture of the hole on one main surface is larger than the aperture of the hole on the other main surface, the internal wall of the hole is covered with an insulation film and at least a part of the insulation film covering the internal wall is covered with a conductor. CONSTITUTION:On the surface of a semiconductor substrate 40, a group of elements has been formed by selective doping, etc. A through-hole is provided in a part of the substrate and the through-hole consists of a smaller hole 41 and a larger hole 42. The internal surface of the through-hole is covered with a comparatively thick insulation film 43 such as an oxidized film, a conductive layer 44 formed in the through-hole and the semiconductor substrate 40 are electrically insulated and simultaneously, the parasitic capacity is reduced. The conductive layer in the through-hole is extended at the boundary of the smaller hole 41 and the larger hole 42, is formed a bonding pad 45 for the bottom surface of a chip and on it, a downward solder bump 46 is formed. The conductive layer 44 in the through-hole is connected to a bonding pad 48 against the upper surface of pitch through a multilayer wiring layer 47 at the side of the surface where the group of element is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the structure of a semiconductor integrated circuit formed by stacking semiconductor integrated circuit chips.

[Background of the invention]

Advanced electronic circuit systems such as computers have traditionally been constructed using high-density integrated circuit (LSI) packages as units, arranged in large numbers on printed circuit boards, and then connected to multiple printed circuit boards. . A more advanced system consists of a multi-chip module as shown in Figure 1, which shortens the wiring length to improve the degree of integration and reduces wiring delays to increase speed. In the multi-chip module shown in the figure, each L'SI chip 11, 11', 11' has a layer 12 on which elements are formed.
The bonding pads 13 provided on the peripheral edge of the chip face downward and are connected to the bonding pads 15 provided on the multilayer wiring ceramic substrate 14 by a known face-down bonding technique.

This multi-chip module does not require thin metal wires for bonding, and each chip is fixed to the multilayer wiring board by solder, which has many advantages such as packaging density and system reliability.

However, in these conventional mounting methods, starting from a completed LSI chip, bonding pads were provided only at the periphery of each chip, and connections between chips were once made via a multilayer wiring board. There was also a limit to shortening the wiring length. That is, with this method, it was not possible to transmit signals between chips over a distance shorter than the wiring length obtained by arranging the chips in a planar manner.

As a method for transmitting signals between chips over a distance shorter than the wiring length obtained by arranging chips in a planar manner, there is a chip stacking type integration technique illustrated in FIG. 2. In this example,
LSI chip 21.21'.

A layer 22゜22 on which a group of elements is formed on one side of 21'', etc.
', 22#, etc. are provided, and the bonding pad 23 provided on the element layer 22 and the bonding pad 24 provided on the back surface of the chip 21' are connected, and the chip is sequentially bonded in this manner. They are stacked, connected, and mounted on a substrate 25.

In order to form a stacked integrated circuit with such a configuration,
A structure for transmitting signals between the front and back sides of the chip is required, and conventionally a structure as shown in the cross-sectional view shown in FIG. 3 has been used. FIG. 3 shows a cross section of the individual chips before interconnection between the chips. Element groups are provided on the surface of each of the semiconductor substrates 31, 31' constituting the chip by selective doping, and chip through holes 32, 32', etc. are provided in some parts. An insulating film 33.33' made of an oxide film or the like is provided on the surface of the through hole 32.32', and a conductive film 34.34' and a substrate 31.3 are provided on top of the insulating film 33.33'.
1' are electrically separated from each other. On the wiring layer are solder bumps 35 used for interconnection between chips.
35' is formed, and the bump 35' of the lower chip is formed.
is directly opposite the bonding pad 34 extending from the aperture in the upper chip. The size of the solder bump shown in this example is about 20 μm in diameter, which is larger than the surface irregularities and chip warpage that exist on a chip with multilayer wiring, and when the solder is melted, all the bumps on the chip are Care has been taken to ensure that each is in contact with the opposing bonding pad.

In addition, the volume of the through hole was designed to be larger than the volume of the solder pump so that the solder would not come into contact with the solder due to pressure from the pumping pad when the solder is melted by hot pressure welding.

However, in the illustrated structure, in order to increase the internal volume of the through hole, for example, in the case of a 50 μm thick semiconductor substrate, it is necessary to form the through hole with a diameter of 10 μm or more, which impedes the improvement of the degree of integration. was. In addition, since the solder pump is formed only on one side of the semiconductor substrate, depending on the surface condition of the opposing bonding pad, a connection failure may occur during thermocompression bonding, causing some reliability problems. .

[Purpose of the invention]

An object of the present invention is to further improve the structure of such a semiconductor element that realizes chip stacking, and to provide a means for ensuring reliable chip connection and application to highly integrated chips.

[Summary of the invention]

The present invention provides solder pumps on both opposing bonding pads in order to connect chips to each other reliably and in a self-aligned manner, and in order to prevent side leakage of the bumps, solder pumps are provided on the back side of the chip with respect to through holes. It is characterized by a structure in which a larger opening is provided on the side than on the front side. With this structure, the opening on the surface side of the through hole can be reduced to the necessary minimum, the active element area on the substrate surface can be expanded, and a method can be provided in which a more highly integrated LSI can be applied to chip integration.

[Embodiments of the invention]

The present invention will be explained below based on Examples. FIG. 4 is a cross-sectional structural diagram of an LSI chip implementing an embodiment of the present invention.

Element groups are formed on the surface of the semiconductor substrate 40 by selective doping or the like. A through hole is provided in a part of the substrate, and the through hole is composed of a detail 41 and a thick part 42. The inner surface of the through hole is covered with a relatively thick reinforcing film 43 such as an oxide film, which provides electrical insulation between the conductor layer 44 formed inside the through hole and the semiconductor substrate 40, and at the same time reduces parasitic capacitance. ing. The conductor layer inside the through hole widens at the boundary between the through hole detail 41 and the through hole thick portion 42 to form a bonding pad 45 for the bottom surface of the chip, and a downwardly directed solder bump 46 is formed on top of the bonding pad 45 . The through-hole conductor [44 is connected to a bonding pad 48 on the top surface of the chip via a multilayer wiring layer 47 on the side where the element group is formed, and an upward solder bump is formed on the bonding pad 48.

C and D shown in FIG. 4 indicate conductor portions within the multilayer wiring layer for transmitting signals to the gate of the element. In the example shown in FIG. 4, the through-hole wiring connects the upper solder bump 49 and the lower solder bump 46, and is connected to one output of the element, but of course this configuration is not limited. Needless to say, any input/output can be connected to the upper and lower solder bumps via the multilayer wiring N47.

Although FIG. 4 shows one through hole and one set of upper and lower solder bumps, in the present invention, a large number of these through holes and bumps are formed.

FIG. 5 shows a partial cross-sectional view of a case where a plurality of integrated circuit chips provided by the present invention are stacked.

The details of the through hole and the isolation insulating film are omitted here. Integrated circuit chips 51.51', 51'' with solder bumps formed above and below through through holes.

51 nl etc. and keeping the temperature above the melting point of the solder, the solder bumps facing each other at the connection part are easily fused, and the cross-sectional shape of the fused part 52, 52' etc. becomes concave as shown in the figure. By adding +i to the size of the pointing pad, the volume of the solder bump, the depth of the thick part of the through hole, etc.
Surface tension acts effectively and absorbs the misalignment within the size of the solder bump, rearranging the integrated circuit chip in a self-aligned manner.

It is recognized that this effect is greater as the number of bumps in the chip increases. The fused portion, which is resolidified by cooling, physically connects the integrated circuit chips to each other and provides electrical connections for signal transmission. Electrical connections may be made through the fused portion and through-hole conductors so that the upper and lower integrated circuit chips are at the same potential, or may be connected to other fused portions via multilayer wiring layers 53, 53', etc. In some cases, it may be connected to the other, or it may be simply a physical connection.

The fused and integrated integrated circuit chip group is connected to a multilayer wiring board 54, and signals are output to the outside via this multilayer wiring board. Although the example of FIG. 5 focuses on one set of solder bumps on the front and back sides of an integrated circuit chip for the sake of simplicity, in reality, a large number of such bumps are formed on an integrated circuit chip.

An example of the manufacturing process for forming the structure shown in FIG. 4 will now be described with reference to FIG. 6.

In this example, through-hole formation is performed in two stages.
The first stage is at the beginning of the process, before the formation of the device layer, and the second stage is after the formation of the device layer. This process is shown in Figure 6 (a).
To explain in order, first, a Si dry etching mask material 60 such as 5 in 2 is placed on the St wafer 600.
1 and open a portion that will become a through hole in the future. Next, as shown in (b), this portion of Si is etched by a known dry etching technique to form a nearly vertical wall surface.
A hexagon 602 of about 15 μm is formed. Next, as shown in (c), a thin film 603 of Si and N4 is formed by directional deposition, and an oxide film 604 is grown only on the sidewalls by selective oxidation. This 5i02 film 604 will serve as an insulating material for the through hole in the future. Next, as shown in (d), vapor phase chemical deposition (C
Highly doped polycrystalline 5i605 is formed by VD) method to backfill the through holes and form a planarization film.

For this purpose, CVD is repeated several times, and if necessary, a flattening sputtering process is performed. Normally, when the hole diameter is about 1 μm, sputtering is not necessary. Next, as shown in (E), the polycrystalline Si is etched away leaving a region containing the through holes. This state is the same as the initial state when forming a normal integrated circuit (LSI), and by appropriately patterning the St, N4 mask 603, the multilayer wiring layer shown in (c) surrounded by a dotted line is formed according to the conventional LSI manufacturing process. An element layer containing the following can be formed. If necessary, by further forming Si and N4 layers in the state (e), it is possible to avoid reduction in the polycrystalline layer due to the difference in oxidation rate.

Up to this point, a Si wafer with a thickness of approximately 500 μm, which has been used in a conventional LSI process, is used. Next, a through hole is formed in the lower half and the overall thickness is reduced in order to reduce the laminated thickness, resulting in the state shown in g). The thickness at this time may be about 50 μm, for example, so that warpage caused by device layer formation does not interfere with subsequent steps. Furthermore, if necessary, a method may be used in which only the peripheral portion is left thick and only the central portion is made thin. In the former case, it can be formed by mechanical polishing, but in the latter case, it is necessary to use etching or ion silling, but it is easier to work if the peripheral edge remains thick when forming the bump. is good. However, this choice is not essential to the invention.

Next, an etching mask material (not shown), such as 5in2 or AQ, is applied to the back surface, an opening is formed on the back surface in accordance with the pointing pad position on the front surface, and the silicon layer is etched by dry etching. Etching (
As shown in h), so that the bottom of the through hole is exposed,
A thick portion 607 of the through hole is formed. The major diameter of this through hole is less than 1/2 of the interval between 1 through hole, but in practical use it is 30-. 5
The depth may be 0 μn1, which is about the same as the depth. Further, Si and N4 remaining at the bottom of the through-hole details are also removed to expose the polycrystalline St filled in the through-hole details.

Next, as shown in (S), CVD 5 inch
, and remove the bottom part of the through hole using photolithography to form a hole 609 (=1 contact with the back surface). Note that since this contact hole 609 is formed at the bottom of a large step, optical lithography using a normal resist method is used.
However, it is possible to easily form this by using a focused ion beam.

Next, a metal coating for forming a pointing pad is applied to the back surface of the wafer, and a pointing pad 6]0 is formed by patterning as shown in FIG.

Incidentally, the following steps are naturally performed with a protective film formed on the surface layer. The surface bonding pad may be formed in the (f) step, or may be formed in the (n) step. A solder layer is formed on the bonding pads formed on the front and back surfaces by a known technique such as plating, and bumps 611, 611' are formed by heating. Note that solder bumps are not formed at this stage.
Although it is more convenient in terms of process to heat the chips after stacking them to make them spherical and to perform a fusing process at the same time, this example is given here to match the shape with the example cited earlier. This final shape (N) is equivalent to that shown in FIG. 4, and chips are stacked using this as a basic unit.

The present invention relates to such a basic shape for stacking chips, and is not limited to the form illustrated in FIG. 4, nor is it formed only by the steps illustrated in FIG. 6. Another embodiment is shown in FIG. 7 to illustrate this. In this case, the basic structure is the same as the embodiment shown in FIG.
etc. have different cross-sectional shapes. In this case, the thick part of the through hole is formed by depositing a 5in2 film on the back surface of the wafer 72 to form an opening, and then performing anisotropic etching using a known alkaline solution.
(111) Utilizes pyramid-shaped pits formed on crystal planes. [Effects of the Invention] As described above, according to the present invention, a stable and advanced process is possible when forming a chip-stacked monolithic circuit. A through-hole structure with high yield can be provided.

Although the present invention has been explained using a Si semiconductor material as an example, according to the gist of the invention, the material is not limited to St, but may also be a material such as GaAs, ■■ compound semiconductor, or ■■
Needless to say, the present invention can be applied to compound semiconductors, etc., and can also be applied to integrated devices made of composite chips made of these materials.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view showing conventional flip chip pointing, Fig. 2 is a cross-sectional structure diagram of chip stacking, Fig. 3 is a cross-sectional view of a chip with a conventional through-wiring structure, and Fig. 4 is a cross-sectional view of a chip with a conventional through-wiring structure. A cross-sectional conceptual diagram of an embodiment of a chip having a through-wiring structure, FIG. 5 is a conceptual diagram showing a cross-sectional structure when chips according to an embodiment of the present invention are stacked, and FIG. 6 shows a structure of an embodiment of the present invention. FIG. 7 is a sectional view showing another embodiment of the present invention. 40...Substrate silicon, 4■...Details of through hole, 4
2...Thick part of through hole, 44...S electric body, 45.48
River ponding pad, 46.49... solder bump,
47...Element layer including multilayer wiring. 1st man 2nd figure 5 3rd prisoner (A) 4th bacterium 5th figure 6 bacterium

Claims (1)

[Claims] 1. In an integrated circuit formed by laminating a plurality of semiconductor substrates,
The semiconductor substrate is provided with a front and back through hole in which an opening on one main surface is larger than an opening on the other main surface, and the inner wall of the through hole is covered with an insulating film, and the inner wall of the through hole is covered with an insulating film. A laminated semiconductor integrated circuit device having a structure in which at least a portion thereof is covered with a conductor. 2. The laminated semiconductor circuit device according to claim 1, having a structure in which at least a portion of the through hole whose inner wall is covered with an insulating film is filled with a conductor.