JPS60160161A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To obtain a high resistor part using short polycrystalline Si layers are used for a load resister, metal wiring layers thereon the electric sourcevoltage supply level is given, are provided in a memory cell, and high resistance polycrystalline Si layers are directly connected to this through contact holes. CONSTITUTION:The first metal layer 21 thereon the electric source voltage VCC is given, is connected to high resistance loads R1 and R2 which are composed of the second polycrystalline Si layers, and the other ends of these resistance are connected to the second direct contacts 231 and 232 and to the diffusion layers through the first direct contacts 241 and 242. In this case, Bi is a bit line made of the second metal layer, 25 is the electric source line VSS, 26 is the first polycrystalline Si layer, 27 is non-doped the second polycrystalline Si layer, and 28 is an insulation film. In such a manner, there is no need to provide the low resistance area on the polycrystalline layer 27, and a high resistance load can be obtained in a short length accordingly.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor memory, particularly an MO8 type static memory cell, which uses a high-resistance polysilicon layer, which is currently mainly used, as a load resistance. It is used as high-density memory.

[Technical/technical background of the invention and its problems]

The memory cells of this type of memory are enhancement type N
Channel MO8) Consisting of a transistor and a high-resistance polysilicon layer, it is called an E/R cell, and the peripheral circuitry is of course N-channel type static memory composed only of N-channel MOS transistors.
It has also come to be widely used in memory cells of 0MO8 type static memory composed of.

FIG. 1 is a circuit diagram of the N-channel static memory cell, and FIG. 2 is a plan view of its integrated circuit pattern.
R, is a load consisting of a high resistance polysilicon layer, Tt #
Tt is a driving transistor, 'r,y T4 is an access gate. Also, B and B are bit lines made of metal (aluminum), 1 is a word line made of first layer polysilicon, and 2 is a power supply vCC line (made of second layer polysilicon).
(low resistance region), 3 is a power supply consisting of an N diffusion layer Vsst<
It is a line.

By the way, the high resistance load elements R,,R, used in the high resistance polysilicon load type memory cell are interposed between the storage node of the memory cell and the power supply Vcc line 3, and hold the charge of the logic 11 level storage node. have a function. In the conventional technology, an impurity (
A step of doping with phosphorus (usually using phosphorus as an N-type impurity) is required, and the second layer polysilicon portion, which has a lower resistance in this way, is used as a power supply Vcc line. Therefore, in this prior art, the high resistance load R1yR1 portion and the low resistance wiring 3 are formed adjacent to each other on the same second polysilicon layer.

As is well known, the second layer of polysilicon is formed by selectively depositing or ion-implanting an impurity (for example, phosphorus) into a polysilicon layer that does not contain any impurities, and then performing a heat treatment process to activate the impurity in the polysilicon. A method has been adopted in which high-resistance portions and low-resistance portions are created separately in the polysilicon layer. However, in the process of heat-treating polysilicon to lower the layer resistance of the low-resistance portion to a practical value, that is, several tens of Ω/D or less, the deposited impurities are activated and simultaneously diffused into the polysilicon. breath,
The diffusion distance Xj is usually about 1 to 2 μ. FIG. 3 shows this situation as a sectional view. In the figure, 11 is the second layer polysilicon portion, 12 is the impurity deposit region, 13 is the impurity diffusion region, 14 is the first layer polysilicon, 15 is the field oxide film, 16 is the N diffusion layer, and 17 is the semiconductor substrate. .

In a high-resistance polysilicon load type memory cell, the resistance value of the high-resistance polysilicon load is preferably a value that provides a charge equal to the sum of all leakage charges at the storage node of the memory cell when the memory cell is at rest. However, the leakage charge increases depending on variations in the manufacturing process or the existence and severity of various defects, so it is usually necessary to have a considerable margin in the amount of charge that can be supplied by a high-resistance load, including manufacturing defects. There is a margin of about two orders of magnitude for the leakage charge in the chip, which is not a problem. Taking a 64Kt' memory as an example, by using a high resistance load of about 1000Ω, a quiescent current consumption characteristic of about 3 μA at 5V is achieved. In order to create a high resistance value of around 100 GΩ in the second layer of polysilicon in the memory cell, a high resistance region of a certain required L/W (L is the resistance length, -, W is the resistance width) must be secured. Therefore, efforts are being made to increase the resistance value by making L as long as possible. Here, L refers to the effective high resistance region in FIG.
-2Xj', and if Xj is large, it becomes difficult to create a high resistance region.

Another difficulty with the conventional technology is that the second layer of polysilicon 11
When etching, a high-resistance region not doped with impurities and a low-resistance region doped with impurities coexist, and the difference in etching speed between the two causes differences in the finished dimensions of the pattern. As is well known, low-resistance polysilicon with impurities diffused therein has an etching rate several times faster than high-resistance polysilicon with almost no impurities diffused therein. In memory cells that require high-density t4 turning, the difficulty of overcutting becomes a very serious problem and has the potential to affect manufacturing yields.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and in creating a high resistance polysilicon load of a high resistance polysilicon load type memory cell, a high resistance portion can be created with a shorter polysilicon load resistance length compared to the conventional example. Furthermore, no impurities are doped into the high-resistance polysilicon layer at the time of etching it, so the etching rate in the valleys of the polysilicon layer is uniform, compared to conventional methods. The present invention aims to provide a semiconductor memory cell that allows high-density processing to be performed more uniformly and at a high yield.

[Summary of the invention]

As mentioned above, in conventional memory cells, the second layer polysilicon is divided into a high-resistance region and a low-resistance region, and the power supply line within the memory cell is routed using the second-layer polysilicon in the low-resistance region. A load resistor was created in a high resistance region of polysilicon. Therefore, the power supply line and the high resistance load are connected without any contact hole. On the other hand, the present invention is characterized in that a metal layer serving as a power supply line and a high resistance polysilicon layer are connected through a contact hole without creating a low resistance region in the /+7 silicon layer.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Fourth
The figure is a circuit diagram showing the same embodiment, Figure 5 is a plan view of the integrated circuit and turns, and Figure 6 is a cross-sectional view thereof, which correspond to those in Figures 1 to 3. Since this is an example of a case, corresponding parts are given the same reference numerals and the explanation FJA is omitted.
I will explain the characteristics. The feature of the present invention is that the first layer metal (aluminum) 21 to which the power supply voltage vCC is applied is
are directly connected to high resistance loads R, , R, of the second layer polysilicon through contact holes 22. The other end of this resistor is connected to the second direct contact (first layer 4e
Contact between polysilicon layer and second polysilicon layer) 2
3. .

23, and the first direct contact (contact between the first polysilicon layer and the diffusion layer) 24. .

24, to the diffusion layer of the transistor. 4 to 6, Bi and Bi are bit lines made of second layer metal, and 25 is a power supply Vss made of first layer metal.
line, 26 is the first polysilicon layer, 27 is high resistance R1,
28 is an insulating film, which is a second-node polysilicon which is not doped with a -cut impurity to achieve Rt.

With the above configuration, since the first layer metal 21 is directly connected to the high resistance load: Rt-Rt of the second layer polysilicon through the contact hole 22, the process of creating the high resistance polysilicon load can be easily There is no need to create a low resistance region on the second polysilicon layer 27 as shown in FIG. cell is obtained. In addition, since it is not necessary to etch areas where the impurity concentration is non-uniform in the second layer polysilicon 27, the etching conversion difference does not become non-uniform depending on the region and adversely affect the manufacturing yield. Fine turning of polysilicon becomes possible. Also, as before, 2
It becomes possible to omit the photolithography process for dividing the high-resistance load portion of the polysilicon layer and the low-resistance region connected thereto, and the step of doping the low-resistance region with impurities.

Also, as you can see from Figure 2, in the conventional manufacturing process (2 layer policy) 5.7 / 1 layer metal), the power supply line 3 is routed with metal! This is impossible because the wiring would cross the bit lines B and B on the same plane.If you try to wire the power supply line 3 in the same direction as the bit lines B and B to avoid this, the cell size Or it gets bigger. Therefore, in the present invention, by introducing a second layer of metal, it is possible to prevent Bs and B from crossing on the same plane, so the above problem is solved.Therefore, the present invention takes advantage of the advantages of two-layer metal layering. It is possible to provide a memory cell that takes full advantage of the

Furthermore, in the present invention, when the metal layer and the high-resistance polysilicon layer are brought into direct contact, a potential barrier exists at the interface between the two, and this varies depending on the polysilicon deposition conditions and is difficult to control. 0~0.
The voltage is as small as about 5V, and poses no practical problem.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to create a high resistance portion with a shorter polysilicon load resistance length than in the past. It is possible to provide a semiconductor memory cell that has advantages such as the etching rate of the silicon layer is uniform in all parts without being affected by the concentration, improving manufacturing yield, the process is simple, and the cell size can be minimized. .

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a conventional memory cell, Fig. 2 is a Noreen plan view of the same circuit, and Fig. 3 is a sectional view showing a part of the same circuit.
FIG. 4 is a circuit diagram of an embodiment of the present invention, FIG. 5 is a schematic plan view of the circuit, and FIG. 6 is a sectional view showing a part of the circuit. R,,R,...High resistance polysilicon layer load, T1~T
4...Transistor, 21...1st layer metal, 22
...Contact hole, 27...Second layer polysilicon. Applicant's agent Patent attorney Suzue TakehikojFigure 11; 1]' 3m I4rR

Claims (1)

[Claims] A pair of inverters consisting of a high-resistance polysilicon layer load and a transistor are cross-coupled between the inputs of 10,000 and the output of the other, and an access gate is connected to the output of each inverter to provide a memory cell and power supply voltage. A semiconductor memory cell characterized in that a metal wiring layer provided with a level is provided in the memory cell, and the high resistance polysilicon layer is directly connected to the metal wiring layer through a contact hole.