JPS60160099A - Compensating circuit of holding voltage - Google Patents

Abstract

PURPOSE:To improve the maintenance characteristics of the holding voltage and to suppress the variance of voltage due to the variance of elements, by compensating the leakage current of a holding a capacitor by a current mirror circuit when an APC wave detection output is held. CONSTITUTION:When an FET-Q11 is turned off, a current flows to the collector of an FET-Q20 in response to the current supplied from capacitor C11. In this case, a current flows to the base of a Q21 in responsed to the emitter current of the Q21. Then a prescribed current flow to the collector of a Q18 which serves as a drive stage of a current mirror circuit. As a result, a Q19 serving as an output stage of the current mirror circuit is driven by the Q18. A current equal to the base current of the Q21 flow to the collector of the Q19 and therefore flows to the C11. Thus the base current of the Q20 which is leaked out of the C11 is compensated. Thus a fixed level of holding voltage is delivered from the emitter of the Q20.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The invention relates to a hold voltage compensation circuit that improves the performance of maintaining the hold voltage during the hold period of a sample-and-hold circuit, for example. [Technical background of the invention and its problems] ] This is a circuit that holds this signal information until the next sample period. In order to extract the signal information during this hold period, the output terminal of the sample and hold circuit is connected to the next stage. There is no problem if the input impedance of this next stage circuit is infinite, but if the impedance is finite, there is a problem that the hold voltage will not be accurate or preferential depending on the above-mentioned cycle.

The conventional sample-and-hold circuit will be explained below with reference to FIGS. 1 and 2.・The sample shown in FIG.
The hold circuit is a capacitor ClIC'! ! This circuit holds the sample voltage as a charge.

That is, signal information to be sampled is applied to the input terminal Pl, and during the sample period, the switch SWt is closed and the signal information is sampled to the capacitor C1.On the other hand, during the hold period, the switch sw1 is opened and the signal information is applied to both ends of the capacitor C1. This is a circuit in which voltage is transmitted to the next stage circuit (not shown) via transistor Q1.

During this hold period, the charge in the capacitor C1 is discharged via the transistor Ql to the next stage circuit via the output terminal P2. Normally, the input impedance of the next-stage circuit is relatively high, so the current flowing into the base of the transistor Q1 (pedestal current IBI) is equivalent to the input current to the sixth-stage circuit.

Therefore, when the sample pulse (FIG. 2a) that defines the opening and closing of the switch SW1 indicates the sample period (t8), the hold voltage (FIG. 2b), which is the signal information held as the charge in the capacitor C1, is: Hold period (th)
The base current Ial decreases as the base current Ial leaks, and correct signal information cannot be maintained.

Furthermore, even if the pace current IBI flowing out from capacitor 0 is set small, the pace current IBI will fluctuate due to variations in the emitter current of transistor Q1 and variations in the current amplification factor (hereinafter referred to as β), and the hold voltage will be correct. I can't hope to maintain it.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a hold voltage compensation circuit that improves the performance of maintaining a hold voltage held during a hold period and suppresses fluctuations in the hold voltage due to variations in elements.

[Summary of the invention]

In this invention, the discharge current leaking from the hold voltage holding circuit that holds the sample signal supplied during the sample period to the pace of the emitter-follower type output transistor is controlled by the current mirror circuit by a current corresponding to this leakage current. The above object is achieved by driving a drive transistor and compensating the current outputted by the drive transistor by driving the output transistor of the current mirror circuit in a feedback manner.

[Embodiments of the invention]

An embodiment of the hold voltage compensation circuit of the present invention will be described below with reference to FIG.

FIG. 3 shows a hold voltage compensation circuit applied to a sample and hold circuit of an APC detector stage in a color signal processing circuit of a television receiver. The hold voltage compensation circuit shown in this embodiment is a killer detector stage or PALS
It can also be applied to the sample and hold circuit of the ident detector stage in a SECAM system.

In FIG. 3, a transistor Ql and a resistor Ru form a constant current source, and a constant current is supplied only during a sample period by a sample pulse applied to a terminal Pi. In addition, the transistor Qu(illt), bias power supply Vau, and Vmi constitute a differential amplifier type detection circuit, and the terminal P12.R
The input signal from s is multiplied and detected only during the above sample period,
Generates the information to be sampled. As the active load of this detection circuit, a current mirror circuit is connected to the transistor Qllll.
, Q19 @The detection output of the above-mentioned ridge wave circuit is the transistor Ql! l, Ql? is taken out from the collector of the capacitor Cu, is held as a charge in the capacitor Cu, and is connected to the terminal P via the transistor Q20 during the hold period.
It is output from 14. In addition, the transistor Q21 has a base current I Bll that flows out as a leakage current from the capacitor Cs1 to the transistor Q20 during the hold period.
This is a transistor that compensates for

In the hold voltage compensation circuit having the above configuration, the terminal P12
The chroma signal including the burst signal is boosted by the VCO.
A subcarrier from L (not shown) is applied to terminal P.
The sample pulse IIK is applied in synchronization with the arrival period of the burst signal, and defines the sample period and the hold period. A sample pulse is input to the pace of transistor Q1, and transistor Qll is turned on. The operation of the period will be explained. At this time, the detection circuit outputs the output of transistor Q14. Detection current Io+4 in the collector of Q16
I, transistor Qls, Ql? Detection current 0-Δi is supplied to the collector of . However, 0 indicates the DC current of the detection circuit when there is no signal, and 2 indicates a current proportional to the phase difference between the burst signal and the subcarrier. Here, transistor Q18 . Ql
If the current amplification factor β of G is high and the pace current can be ignored, the detected current I o+j I flows through the collector of the transistor Qss, and a current equal to this flows through the collector of the transistor Q1.
It flows to 9th. Therefore, the snow of transistor Qse≠奔#poison mother collector current I6+j s and transistor Qls,Q
Common collector current Io of iy - difference current of jI dIa=-(Io-)yI)-(to-jI)=2Δ
・・・・・・・・・・・・・・・(1) flows to the capacitor C1l. At both ends of this capacitor CIl,
A voltage proportional to the charged charge appears.

Next, the operation during the hold period when the burst signal period, which is the sample period, ends and the transistor Qst is turned off will be described.

Since the transistor Qu is in the off state during the hold period,
No current output appears in the detection circuit, and the current mirror circuit also operates from the inactive capacitor c11 to the transistor Q15.
The current flowing to Ql is cut off, and the charge on capacitor C1l is held. 0 A voltage proportional to the charge charged on capacitor C1l is output from terminal psa via output transistor Q20. However,
The charge of the capacitor C1l gradually leaks as the pace current IBII of the transistor QX+, and the correct hold voltage is not maintained.The operation of the current mirror circuit and the compensation transistor Q21 for compensating the pace voltage IBII will be explained next.

A current βIBII flows from the capacitor C1l to the emitter of the transistor Q21, that is, to the collector of the transistor Qso, corresponding to IBII as a transistor Q-pace current. Here, the transistor QIKISQz1
Let β be the current amplification factor of the transistor Q21. Corresponding to the emitter current /IBII of this transistor Q21, a current of s+/I Bls flows to the base of the transistor Q2, and flows to the collector of the transistor Q1g, which is the drive stage of the current mirror circuit. Also, a current of 1+/I Bll flows. Therefore,
Transistor Q19 which is the output stage of the current mirror circuit
is driven by transistor Q18, and a current equal to IBI□ flows through its collector. Therefore, the current 1+/IBII flows into the capacitor CuK to compensate for the pace current IBII leaking from the capacitor C1l, so that a hold voltage of 9 is output from the emitter of the transistor Q20 for a constant hold period.

Note that during the sample period, the capacitor C
The charge leaking from 1l is compensated for, but this leakage charge is very small compared to the signal to be sampled, and the sampling period is short, so the fluctuation due to the leakage charge is not a problem.9 As explained above, t1 According to this embodiment, it is possible to compensate for the current leaking from the capacitor that holds the hold voltage during the hold period, so that the maintenance performance of the hold voltage is improved.

Further, even if the leakage current changes due to variations in the element values of the output transistors, a current equal to this leakage current is compensated, so that the hold voltage does not vary due to variations in the element values.

Next, another embodiment of the present invention will be described with reference to FIG. 4. ◎ FIG. 4 shows a hold voltage compensation circuit applied to a capacitively coupled DC regeneration circuit.

In FIG. 4, transistor Qs1 and resistor Rst form a constant current source, and a gate pulse is applied to terminal P31. Further, the transistors Qsg, Qss and the bias power supply V Bll constitute a differential amplifier, and a current mirror circuit serves as an active load of the differential amplifier between the transistors Qs4 and Qs4. ◎The transistor Q-Pace of the differential amplifier is configured by the transistor Q-Pace, and the TV engine signal is applied from the terminal pst via the capacitor Css. It is output from the terminal paa via Qas. Transistor Q37 is a capacitor Ca
Base current lB5 flowing from transistor Qsd/C from 1
This is a transistor that compensates for 1.

In the DC reproducing circuit configured as described above, a television video signal to be DC-reproduced in accordance with the pedestal level is applied to the terminal P32. First, a case will be described in which a gate pulse synchronized with the pedestal period of this video signal is applied to the terminal Pas.

During the input period of this gate hullless transistor Qa1 is turned on, and the differential amplifier and current mirror circuit operate. Occurs at the pace of transistor Q32,
A voltage equal to the difference voltage between the pedestal level of the video signal applied to the terminal P32 and the potential VB31 is applied to the capacitor C31.
occurs in That is, the capacitor tcsx is clamped to the pedestal level, and the gate pulse is applied to the terminal ps.
1. At this time, transistor Q31 is in the off state, so transistor Q32. Q33 is also turned off. On the other hand, the video signal inputted from the terminal Pu is outputted to the terminal pss via the capacitor, the sensor 1, and the output transistor Qss.゛At this time, the video signal is clamped by the voltage difference occurring across the capacitor C31 (7), so a video signal whose pedestal level is equal to the potential VB31 always appears at the base of the transistor Qu, and the DC component is reproduced. . However, the output transistor Q
Since the base current 1B31 flows through ss, the electric charge of the capacitor Cat leaks, and the voltage held by the capacitor C31, that is, the pedestal level, gradually decreases.

Compensation for the leakage of the capacitor C31 due to the base current Inal of the transistor Qas is performed by the current mirror circuit and the compensation transistor Q37 as in the previous embodiment.

That is, in response to the current lB51 leaking from the capacitor Cal as the base current of the transistor Q3g, βlB51 flows to the emitter of the transistor Q37, and 1+/
In addition, the same current flows through the drive stage transistor Qss of the current mirror circuit and drives the output stage transistor Q34, so the current '1B51 flows into the collector Cal of the transistor Qas, and the capacitor C311+β Since the base current IB51 leaking from the capacitor Csx is compensated for, the pedestal level, which is the hold voltage of the capacitor Csx, does not vary during the non-pedestal period.

As explained above, according to this embodiment, the pedestal level of the video signal can be clamped with high accuracy.

In addition, in the previous embodiment and this embodiment, the hold voltage can be compensated without increasing a new current, so that they are particularly suitable for integrated circuit implementation.

〔Effect of the invention〕

According to the present invention, the hold voltage maintenance performance is improved and an accurate hold voltage can be output. Further, it is possible to eliminate fluctuations in the hold voltage due to variations in elements.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram for explaining a sample-and-hold circuit, FIG. 2 is a waveform diagram for explaining FIG. 1, and FIG. 3 is a circuit diagram showing an embodiment of the hold voltage compensation circuit of the present invention. 4 are circuit diagrams showing other embodiments of the present invention. C1l, C31... Capacitor pH~Ra
, P31~Pas...Terminal Qll A+Q21
．． Q31-Q37...Transistor R1? -R
12, Torque loss 2... Resistance Figure 1 Figure 2 = T: ■ Knee th 4 Ninini Dye μ-1 Figure 3'

Claims (1)

[Claims] An input signal is applied to the input end, and a sample signal generation circuit generates a sample signal to be sampled at the output end in response to a sample pulse input to the gate end. a hold voltage holding circuit that holds charges corresponding to the supplied sample signal during a hold period that is a period other than the sample pulse; and a hold voltage holding circuit that outputs a voltage corresponding to the charges held in the hold voltage holding circuit in an emitter follower form. a first transistor and a collector-emitter current path connected in series to the collector-emitter current path of the first transistor;
A current corresponding to a leakage current caused by the charge held in the hold voltage holding circuit leaking to the pace of the first transistor flows through the pace of the second transistor during the hold period, and a pace current of this second transistor causes a current to flow through the pace of the first transistor. A current mirror circuit having a third transistor which is driven and a current corresponding to the pace current flows through the collector-emitter current path by a mirror operation, and the collector-emitter current of the third transistor of this current mirror circuit. A hold voltage compensation circuit comprising: a current path that flows through the hold voltage retention circuit to compensate for leakage charge of the hold voltage retention circuit due to the leakage current.