JPS60167382A - Internal matching type fet circuit - Google Patents
Internal matching type fet circuitInfo
- Publication number
- JPS60167382A JPS60167382A JP2318684A JP2318684A JPS60167382A JP S60167382 A JPS60167382 A JP S60167382A JP 2318684 A JP2318684 A JP 2318684A JP 2318684 A JP2318684 A JP 2318684A JP S60167382 A JPS60167382 A JP S60167382A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- wire
- phi
- circuit
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 abstract description 13
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は内部整合型ＦＥＴ回路に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to an internally matched FET circuit.
従来例の構成とその問題点
近年マイクロ波帯におけるＦＥＴの開発は目ざましいも
のである。ところで、とのＦＥＴは大出力化のため、ゲ
ート幅が大きくせねばならず、ＦＥＴの入力インピーダ
ンスが低くなる。更にまた、使用周波数が高い程入力イ
ンピーダンスは低くなる。従って、パッケージの寄生容
量やリードのインダクタンスの影響が大きくなシ、パッ
ケージ外部に整合回路をつけても、整合の帯域がせまく
なシ、整合がと９にくくなる。このためパッケージ内部
に整合回路をつけた内部整合ＦＥ、Ｔが使用されてきた
。このような整合回路は、特に入力インピーダンスが低
くなるため従来入力側に設けられるのが常である。Conventional configuration and its problems In recent years, the development of FETs in the microwave band has been remarkable. By the way, in order to increase the output of the FET, the gate width must be increased, and the input impedance of the FET becomes low. Furthermore, the higher the frequency used, the lower the input impedance. Therefore, the effects of the parasitic capacitance of the package and the inductance of the leads are large, and even if a matching circuit is provided outside the package, the matching band will be narrow and matching will become difficult. For this reason, internally matched FEs and Ts with a matching circuit inside the package have been used. Conventionally, such a matching circuit is usually provided on the input side because the input impedance is particularly low.
第１図は従来の内部整合型ＦＥＴ回路である。FIG. 1 shows a conventional internally matched FET circuit.
半導体チップ１のドレイン、ソースおよびゲートがそれ
ぞれドレインワイヤ２．ソースワイヤ４゜ゲートワイヤ
６によって、ドレイン電極３．パッケージのベース５．
ゲート電極８にそれぞれボンディングされている。また
ゲートワイヤ６にはキャパシタンス７が接続されている
。これは入力側にキャパシタンスを入れてリードワイヤ
のインダクタンスとの組み合せで、半導体チップ１０入
力インピーダンスの複素共役にすることが図られたもの
である。しかしながら、単導体チップ１自体がユニラテ
ラル素子ではなく、パワーＦＥＴのようなゲート幅の広
い素子では、特に大出力をはかってゲートＩ扁をかを多
大きくしていくと入力と出力の間の帰還量もそれに比例
して大きくなる。その結果入力側に整合回路を入れても
、入力の整合がほとんどとれなくなってしまうという問
題があった０
発明の目的
本発明は上記欠点に鑑みなされたもので、入力側の整合
をとることのできる内部整合型ＦＥＴ回路を提供するも
のである。The drain, source and gate of the semiconductor chip 1 are each connected to a drain wire 2. Source wire 4° and gate wire 6 connect drain electrode 3. Package base 5.
They are bonded to the gate electrodes 8, respectively. Further, a capacitance 7 is connected to the gate wire 6. This is intended to create a complex conjugate of the input impedance of the semiconductor chip 10 by inserting a capacitance on the input side and combining it with the inductance of the lead wire. However, the single conductor chip 1 itself is not a unilateral device, and in devices with wide gate widths such as power FETs, especially when aiming for high output and increasing the gate width, the distance between input and output increases. The amount of feedback also increases proportionally. As a result, even if a matching circuit is installed on the input side, there is a problem in that input matching is almost impossible.Objective of the Invention The present invention was made in view of the above disadvantages, and it is difficult to match the input side. The present invention provides an internally matched FET circuit that can perform the following functions.
発明の構成
この目的を達成するだめに、本発明の内部整合型ＦＥＴ
回路は、ＦＥＴと前記ＦＥＴの出力側に設けられた整合
回路とから構成されている。このことにより、容易に入
力側の整合をとることが可能となる。Structure of the Invention In order to achieve this object, an internally matched FET of the present invention is used.
The circuit is composed of a FET and a matching circuit provided on the output side of the FET. This makes it possible to easily match the input side.
実施例の説明 以下本発明の一実施例を図面を参照しながら説明する。Description of examples An embodiment of the present invention will be described below with reference to the drawings.
第２図は本発明の一実施例における内部整合型ＦＥＴ回
路の回路図である。第２図において、半導体チップ１と
して、ゲート幅４．８闇のＧ ａ Ａ ５ＦＥＴ、キャ
パシタンス７は容量１ｏｐＦのＭＯＳキャパシタを使用
した。ワイヤはすべて２０μｍφのＡｕ線で、ドレイン
ワイヤ２は半導体チップ１からＭＯＳキャパシタ７まで
０．５瑞、ＭＯＳキャパシタ７からドレイン電極３まで
０．７ｍｍ、ソースワイヤ４は０．３ｒｎｒｎ、ゲート
ワイヤ６は１．３胴である０
次に、計算機７”／−ミレージョンと測定の結果を次表
に示す。尚、７−ミレージョンはＦＥＴの等節回路モデ
ルに、各デバイスパラメータの値を代入しＳパラメータ
を計算させた。FIG. 2 is a circuit diagram of an internally matched FET circuit in one embodiment of the present invention. In FIG. 2, a Ga A 5FET with a gate width of 4.8 mm was used as the semiconductor chip 1, and a MOS capacitor with a capacitance of 1 opF was used as the capacitance 7. The wires are all Au wires with a diameter of 20 μm, the drain wire 2 has a wire length of 0.5 mm from the semiconductor chip 1 to the MOS capacitor 7, the length from the MOS capacitor 7 to the drain electrode 3 is 0.7 mm, the source wire 4 has a wire length of 0.3 rnrn, and the gate wire 6 has a wire length of 0.5 mm. 1.3 cylinder 0 Next, the results of the measurement using the calculator 7''/-mileage are shown in the table below.The 7-mileage is calculated by substituting the values of each device parameter into the isochoric circuit model of the FET. S-parameters were calculated.
同表において、Ｓ１１は周波数１ＧＨｚ における値で
ある。ＦＥＴのみのときと入力側にＣ−１０ｐＦのキャ
パシタを入れたときと、出力側にキャパシタＣ＝１０ｐ
Ｆのキャパシタを入れたときの８１１を示している。出
力側にキャパシタを入れると８１１が小さくなり、整合
がとりやすくなることがわかる。測定の結果もシュミレ
ーションの通り、出力側にキャパシタを入れると８１１
が小さくなシ、スミスチャートでは内側にはいってくる
ことがわかった。また、Ｓ１１は出力側にキャパシタを
入れると入力側に入れたときよシも小さくできることも
確かめられた。In the same table, S11 is a value at a frequency of 1 GHz. When only FET is used, when a C-10pF capacitor is inserted on the input side, and when a capacitor C=10p is placed on the output side.
811 is shown when a F capacitor is inserted. It can be seen that when a capacitor is inserted on the output side, 811 becomes smaller and matching becomes easier. As per the simulation, the measurement result is 811 when a capacitor is inserted on the output side.
It turns out that the smaller the C, the smaller it will be on the inside of the Smith chart. It has also been confirmed that if a capacitor is placed on the output side of S11, it can be made smaller than when it is placed on the input side.
発明の効果
以上のように構成された出力内部整合型ＦＥＴ回路は、
入力インピーダンスが特性インピーダンスに近いので、
外部回路との整合がとりゃすくなシ、整合の帯域も広が
るので、実装時の組立のばらつきによるミスマツチング
を少なくできる。The output internal matching type FET circuit configured as above the effects of the invention,
Since the input impedance is close to the characteristic impedance,
Since matching with external circuits is easy and the matching band is widened, mismatching due to assembly variations during mounting can be reduced.
第１図は従来の内部整合型ＦＥＴ回路図、第２図は本発
明の一実施例における内部整合型ＦＥＴ回路図を示す。
１・・・・−・半導体チップ、２・・・・・・ドレイン
ワイヤ、３・・・・・・ドレイン電極、４・・・・・・
ソースワイヤ、５・・・・・・パッケージベース、６・
・・・・・ケートワイヤ、７・・・・・・キャパシタン
ス、８・・・・・・ゲートｔ！。FIG. 1 shows a conventional internally matched FET circuit diagram, and FIG. 2 shows an internally matched FET circuit diagram according to an embodiment of the present invention. 1... Semiconductor chip, 2... Drain wire, 3... Drain electrode, 4...
Source wire, 5...Package base, 6.
...Kate wire, 7...Capacitance, 8...Gate t! .
Claims (1)
が同一パッケージ内に封入されていることを特徴とする
内部整合型ＦＥＴ回路。An internal matching type FET circuit characterized in that an FET and a matching circuit provided on the output side of the FET are enclosed in the same package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2318684A JPS60167382A (en) | 1984-02-09 | 1984-02-09 | Internal matching type fet circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2318684A JPS60167382A (en) | 1984-02-09 | 1984-02-09 | Internal matching type fet circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60167382A true JPS60167382A (en) | 1985-08-30 |
Family
ID=12103619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2318684A Pending JPS60167382A (en) | 1984-02-09 | 1984-02-09 | Internal matching type fet circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60167382A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0626028A (en) * | 1992-06-22 | 1994-02-01 | Kowa Kikai Sekkei Kogyo Kk | Sucking up device for surface layer liquid |
-
1984
- 1984-02-09 JP JP2318684A patent/JPS60167382A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0626028A (en) * | 1992-06-22 | 1994-02-01 | Kowa Kikai Sekkei Kogyo Kk | Sucking up device for surface layer liquid |
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