JPS6016655B2 - I/O device access control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an input/output device access control system, in particular, a method for managing the busy state of each device constituting the hierarchical structure when accessing an input/output system having a hierarchical structure. The present invention relates to an input/output device access control method in which a management section is built into, for example, a central processing unit, and the central processing unit accesses an input/output system by referring to the contents of the state management section.

Generally, in a data processing system, a central processing unit, a channel device, an input/output control device, and an input/output device are connected in a hierarchical structure.

When the central processing unit accesses a certain input/output device, it specifies the machine number of the input/output device and also specifies a route such as which channel to use. Control was carried out as follows.

In other words, in the case of the first method, the central processing unit specifies the machine number of the input/output device to be accessed and each device or device group to which the input/output device is accessed, and starts 1/0 (start input/output). issue a command.

'B} If each blind eye can be properly captured and operated by the start 1/0 command, the processing for the start 1/0 command will be completed.

'C' If one of the devices cannot be started due to reasons such as not being available or being busy,
Perform the next process, such as [E-].

If there is another route to the input/output device to be accessed, specify the other route, issue the start 1/0 command again, and perform the above process 'B). For example, if the device that was in the busy state above receives a signal notifying that it has become free, or if it is confirmed that a certain period of time has elapsed, the device will start 1/1 again using the same route as above.
Issue the 0 command and perform the above process [B-]. In the case of the first method described above, it is necessary to check the free status of the specified input/output device and the devices on its path, and it takes a relatively long time to determine the free status. One of the causes is the signal propagation time of the cable connecting the devices.

Furthermore, since the busy state of each device is not managed, a start 1/0 command is also issued to a device that is clearly currently in a busy state due to the start 1/0 command issued just before. That will happen. In order to solve the drawbacks of the first method, the following second method is known. That is, a control table (UCB) is prepared for each input/output device located at the end, and based on the contents of the UCB, a start 1/0 command is issued to the input/output device that is clearly in a busy state. I will refrain from doing so for a while. Note that the second method is the one in which the above-mentioned function is added to the first method. Even in the case of the second method, if devices on the path to the individual input/output devices mentioned above are in a busy state, the start 1/0 command will still be issued many times.

Furthermore, in the first method and the second method, the start 1
Because it takes an undesirable amount of time after a /0 is issued before any device is found to be busy,
A third method is also being considered.

That is, the start command in the case of the third method is start 1/0.
・It is called the F instruction, and the central processing unit starts 1/0・F
After issuing the command to the channel device, the central processing unit immediately enters another processing execution state without waiting for the above-mentioned busy state to become clear. When a busy state is found, the central processing unit is notified of this by an interrupt from the channel side. However, in the case of the third method, it is not known when the above-mentioned interrupt will occur, and the processing may become complicated.

The present invention aims to solve the above points,
In accordance with the system configuration of the input/output system, for example, a state management unit that grasps the busy status of various devices existing in a hierarchy and the hierarchical structure status of various devices is built into the central processing unit, and the central processing unit When accessing the device via a certain route, the contents of the state management section are
The purpose is to check by using an EST command, etc., and then have the central processing unit or upper status management unit issue a start 1/0 command, thereby significantly reducing the number of times the start 1/0 command ends in failure. .

Therefore, the input/output device access control method of the present invention applies to a plurality of central processing units that independently proceed with processing in response to a given process, and to any one of the central processing units, one or more channel devices, including those described above and commonly connected to any or more central processing units, and one or more of the respective channel devices; One or more input/output control devices that can be connected to a plurality of input/output control devices, and one or more input/output control devices that can be connected to one or more of the input/output control devices. In a data processing system having a hierarchical input/output system having a plurality of input/output devices, the channel devices and input/output devices that may be connected to one or more central processing units correspond to one or more of the central processing units. A state management section is provided to store the states of the control device and the input/output device, and the state management section corresponds to each of the channel devices, input/output control devices, and input/output devices that may be connected. a storage unit which is generated by the device and has at least the busy state indication information of each device, the device number of the device, and the device number of the lower device connected to the device; The central processing unit is characterized in that before specifying and issuing a start input/output command to the channel device, the central processing unit checks the contents of the state management section. This will be explained below with reference to the drawings. FIG. 1 shows the configuration of an embodiment of a data processing system to which the present invention is applied, and FIG. 2 shows the configuration of an embodiment of the state management section according to the present invention.

In FIG. 1, 1-0 and 1-1 are central processing units, respectively;
2-1 to 2-3 are processor devices, respectively; 3-1, 3;
-2 is the state management unit referred to in the present invention, 4-1 is absent, and 4-4 is the state management unit according to the present invention.
-3 each represent a channel device (including a channel processor); 5-11 and 5-3 respectively represent an input/output control device; 6-1 and 6-5 represent an input/output device, respectively.

In the present invention, when an input/output system configuration as shown in FIG. 1 is given, the state management section 3-1 is provided with storage units corresponding to the following devices.

That is, channel devices 4-1, 4-2, input/output control device 5
-1, 5-2, 5-3, input/output device 6-1, 6-2, 6
Storage units corresponding to -3, 6-4, and 6-5 are prepared. In addition, the state management section 3-2 is provided with storage units corresponding to the following devices. That is, channel devices 4-3
, the input/output control device 5-3, and the storage units corresponding to the input/output devices 6-4, 6-5 are prepared. Note that information is generally not exchanged between the illustrated state management units 3-1 and 3-2. In the case of the present invention, the state management unit 3 is explained as follows with reference to FIG. 2 corresponding to the configuration shown in FIG.
-1 is used to access the input/output device. FIG. 2 shows the configuration of an embodiment of the state management section according to the present invention. Codes in the diagram: 2-1, 2-2, 1/0 series, 3-1
corresponds to FIG. 1, 7 is an initial setting circuit section (part 1), 8 is an input/output activation command check circuit section (part C), 9 is a register section representing the configuration of the input/output device system (part R), 10 11, 11 and 20 are registers corresponding to the storage unit according to the present invention, respectively. (11') Given the configuration of the input/output system as shown in FIG. 1, the processor unit 2-1 notifies the initial setting circuit section 7 of the configuration of the input/output system, for example.

[21 In response to the above notification, the circuit section (1 section) 7 stores the memory unit 1 in the register section (R section) 9.
0 is prepared, and the status information STS in each storage unit 11 absent/present 20 is set to an empty state (for example, "0").

In addition, each storage unit 11 is not included, and the device 4-
1, 4-2, 5-1, 5-2, 5-3, 6-1, 6-2
, 6-3, 6-4, and 6-5. In each storage unit, A is status information, B is device type information, C is device number information, D is information on the number of lower devices connected to the self, and E is information on the number of lower devices connected to the self. Indicates machine number information. '3' Now, the processor unit 2-1 specifies, for example, the input/output device 6-5, and also specifies the path of the channel device 4-2, the input/output control device 5-3, and the input/output device 6-5, and accesses it. When the processor unit 2-1 intends to execute the program, the processor unit 2-1 checks the contents of the state management section 3-1 using, for example, a TEST command.

{41 Accordingly, the circuit section (C section) 8
Section) Examine the contents of the status information STS in the storage units 12, 15, and 2 in the 9.

'5' If all of the storage units are empty, the contents of the status information STS in each storage unit 12, 15, 20 are set to a busy state (for example, "1"), and the circuit section (
Section C) 8 directly issues a start 1/0 command specifying the input/output device 6-5 and its route to the channel device 4-2 side.

'61 When each device on the route and the input/output device 6-5 starts up normally and the processing corresponding to the access is completed,
The 1/0 system shown in FIG. 2 notifies the circuit section (A section) 10' of this fact.

'7} Accordingly, the circuit section (A section) 10
Part R) Returns the status information STS of the storage units 12, 15, and 20 in the 9 to the empty state "0".

At the same time, the processor unit 2-1 is notified. Shelf In the state where the start 1/0 command is issued by the above process (■), for example, the input/output device 5-3 is in a busy state, and this fact is transmitted from the 1/0 system shown in the diagram to the circuit section (A section) 10.
may be notified. That is, for example, in the case of the input/output configuration shown in FIG. 6-4, and this fact is not notified to the circuit (R section) 9 in the state management section 3-1. In such a case, the illustrated circuit section (
Part A) 1) This will be notified to the processor unit 2-1. '91 At this time, the circuit section (C section) 8 connects the input/output device 6-5 to the input/output device 6-5 via another path, for example, the channel device 4-1, the input/output control device 5-2, and the input/output device 6-5. Access is optional.

When access is made through such a new route, in the circuit section (R section) 9, the storage units 11 and 14 are
, 15, 20 status information STS is busy 1
”). Then, when the processing corresponding to the access is completed, the processing side, as shown in [7},
unit 2-1 is notified and storage unit 11,1
Status information STS 4 and 20 are returned to the empty state. Note that the status information STS of the storage unit 15 is notified from the illustrated 1/0 system to the circuit section (A section) 10 when the processing via the input/output control device 5-3 is completed, and the status information STS is returned to the empty state. ■ Corresponding to the above process ■, the circuit section (
If the C part) 8 does not use the new route as described above or if the new route does not exist, the status information of the storage unit 15 that was previously set to the busy state in the circuit part (R part) 9 is processed. The STS is left busy.

(11) And from the 1/0 system shown in the diagram, the circuit section (A section) 10'
On the other hand, when there is a notification that the input/output control device 5-3, which was in the busy state, becomes free, the circuit section (A section) 10 stores the storage unit 15 in the circuit section (R section) 9. The status information STS is returned to the empty state.

As a result, the circuit section (C section) 8 is connected to the channel device 4.
-2, the input/output control device 5-3, and the input/output device 6-5 issue a start 1/0 command, and at the same time put the status information STS of the storage units 12, 15, and 20 into the idling state. In order for the above-mentioned processing to take place,
The present invention has the following advantages over conventional methods.

That is, (i) Now (a) at timing T, the processor unit 2-1 tries to access the input/output device 6-1 via the channel device 4-1 and the input/output control device 5-1, and then ( b) At timing T2, from processor unit 2-1 to channel device 4-2.
and input/output device 6-2 via input/output control device 5-1.
, and then (c) at timing T3, the processor unit 2-1 attempts to access the input/output device 6-3 via the channel device 4-2 and the input/output control device 5-1. Suppose we did.

Assume that the result of the access corresponding to (a) above is not reflected and a start 1/0 command is issued for the access corresponding to (b) above or the access corresponding to (c) above.

In this case, in the conventional method, for example, the timing Q
The input/output control device 5-1 responds to the result of the access corresponding to (b) mentioned above only at the delayed point in time.
It turns out that it was busy. On the other hand,
In the case of the present invention, when the state management unit 3-1 is checked to make an access at the timing T2, it is immediately found that the input/output control device 5-1 is in a busy state. (i
i) Also, (d) at timing L, processor 2
-1 attempts to access the input/output device 6-4 via the channel device 4-2 and the input/output control devices 5-3, and then (e) at timing T5, the processor
The unit 2-3 attempts to access the input/output device 6-4 via the channel device 4-3 and the input/output control device 5-3, and then (f) the processor unit 2-3 tries to access the channel device 6-4 at timing T6. Assume that an attempt is made to access the input/output device 6-5 via the hawk 4-3 and the input/output control device 5-3. In this case, in the conventional method, the input/output control device 5-3 is busy in response to the result of the access corresponding to (e) mentioned above, only at a delayed point such as timing T6. That will become clear. On the other hand, in the case of the present invention, when the state management unit 3-2 is checked and a start 1/0 command is issued at the timing T5 to perform the access corresponding to the above (e), by the timing t, It is found that the input/output control device 5-3 is in a busy state, and this fact is written in the state management section 3-2. Therefore, in order to perform access corresponding to (f) above, the state management unit 3-
2, it is found that the input/output control devices 5-3 are not in a vacant state. As explained above, according to the present invention, the contents of the state management section 3 can be checked using the TEST command, which is the same as when a processor unit executes a normal command, and only then can the start 1/0 command be executed. is emitted.

Therefore, the frequency of issuing start 1/0 commands in vain is greatly reduced. Furthermore, even in a system in which a channel device, an input/output control device, or an input/output device is commonly used, the likelihood of unnecessary start 1/0 commands being issued as described above is reduced. The state management section may be processed by the main memory and processor unit in the central processing unit 110 or 1, or by using a special stored program processing device, or by using wired logic. You are free to use the equipment.

In addition, in the above explanation, route changes and actual start 1/1
Although the description has been made assuming that the state management unit generates the 0 instruction, it may also be generated by the processor unit 2-1 or the like. Furthermore, although the state management units 3-1 and 3-2 are provided independently in the configuration shown in FIG. 1, a common state management unit may be provided, or both state management units 3-1 and 3-2 may be provided separately. It goes without saying that information may be exchanged between them.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an embodiment of a data processing system to which the present invention is applied, and FIG. 2 shows the configuration of an embodiment of the state management section according to the present invention. In the figure, 1-0 and 1-1 are central processing units, respectively, 2-1 is absent, 2-3 are processor units, and 3-1, 3-2 are state management units, respectively, 4-1 is absent, and 4-1 is not present. 4-3 are respective channel devices; 5-1 to 5-3 are respective input/output control devices;
6-1 None, 6-5 are input/output devices, 7 is an initial setting circuit section, 8 is an input/output start command check circuit section, 9 is a configuration representation register section of the input/output device system, 10 is an input/output device system There is no response receiving circuit section 11, and 20 represents a storage unit. Figure 1, spear 2

Claims (1)

[Scope of Claims] 1. A plurality of central processing units that independently proceed with processing in response to given processing, each of which is connected to any one of the central processing units in a cascaded manner, and which is connected to any one of the above central processing units. one or more channel devices, including one or more channel devices that are commonly cascaded connected to a plurality of central processing units; Data having a hierarchically structured input/output system having one or more input/output control devices and one or more input/output devices connected to one or more of the input/output control devices in a cascaded manner. In the processing system, the channel device may be connected to one or more of the central processing units;
A state management section is provided that stores the state of each of the input/output control device and the input/output device, and the state management section stores the state of each of the channel devices, input/output control device, and input/output device that may be connected. A storage unit is provided correspondingly and has at least busy state indication information of each device, a machine number of the device, and a machine number of a lower-level device connected to the device, and the predetermined input/output device is connected to the device. 2. An input/output device access control method, wherein the central processing unit checks the contents of the state management section before specifying and issuing a start input/output command to the channel device. 2. The input/output device access control system according to claim 1, wherein the state management unit is built in the central processing unit.