JPS6015937A - Cladding material for semiconductor support electrode - Google Patents
Cladding material for semiconductor support electrodeInfo
- Publication number
- JPS6015937A JPS6015937A JP58123649A JP12364983A JPS6015937A JP S6015937 A JPS6015937 A JP S6015937A JP 58123649 A JP58123649 A JP 58123649A JP 12364983 A JP12364983 A JP 12364983A JP S6015937 A JPS6015937 A JP S6015937A
- Authority
- JP
- Japan
- Prior art keywords
- invar
- cladding material
- plate
- invar plate
- electrode material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の背景と目的〕 本発明は半導体支持電極用クラツド材に間する。[Detailed description of the invention] [Background and purpose of the invention] The present invention relates to a cladding material for semiconductor supporting electrodes.
一般に半導体装置では半導体素子と電極材とが半［１］
等により接続された構造となっているが、例えば高集偵
化されたＩＣやパワー素子においては素子からの発熱が
非常に大きい。このため電極材としては電気伝導性の良
いことと共に、素子に発生ずる熱を速やかに放散させる
ために熱伝乃性の良いこと、及び熱衝撃に耐えるために
ｌ’Ｊｌ ｋ張係数が素子との間で極端な差がなく整合
性がとれていること、且つ半導体装置に対して必要な形
状に加工することが容易であること、さらに素子との接
着が容易であること等の性質が要求される。Generally, in a semiconductor device, the semiconductor element and the electrode material are half [1]
However, for example, in highly integrated ICs and power devices, the heat generated from the devices is extremely large. Therefore, as an electrode material, it must have good electrical conductivity, good thermal conductivity to quickly dissipate the heat generated in the device, and a tensile coefficient of l'Jl k that is similar to that of the device to withstand thermal shock. Properties such as consistency with no extreme differences between the two, ease of processing into the shape required for semiconductor devices, and ease of adhesion to elements are required. be done.
この様なことから、一般に電極材としてはＣｕが用いら
れるが、その熱膨張係数は１６．５Ｘ１０−’／℃であ
り、半導体素子の例えばＳｉの３．５ Ｘｌ０−６／℃
と比べれば非常に大きく、昇温次の熱歪差が問題となる
。For this reason, Cu is generally used as an electrode material, but its thermal expansion coefficient is 16.5X10-'/°C, which is 3.5X10-6/°C for semiconductor devices, for example, Si.
This is very large compared to the above, and the difference in thermal strain after temperature rise becomes a problem.
このため、従来は第３図に示されるように、例えばＳｉ
ｌの半導体素子とＣｕ電極材２”の中間に熱膨張係数整
合用のＭＯ３′あるいはＷを挟んで半田付しているが、
このＭＯやＷは資源的に偏在する希少材料であるために
高価であり、またプレスによる紋り加工がほとんど不可
能であるなと半導体装置のように非常に小型で精密性が
要求されるものにとっては成形性が良くないという難点
がある。なお、第３図において、４′は半田付部、５′
はアルミナ絶縁体、６′はＣｕ支持板である。For this reason, conventionally, as shown in FIG.
MO3' or W for thermal expansion coefficient matching is sandwiched and soldered between the semiconductor element 1 and the Cu electrode material 2''.
MO and W are rare materials that are unevenly distributed in terms of resources, so they are expensive, and it is almost impossible to stamp them with a press for very small and precision-required products such as semiconductor devices. However, the problem is that the moldability is not good. In addition, in Fig. 3, 4' is the soldering part, and 5' is the soldering part.
is an alumina insulator, and 6' is a Cu support plate.
このような従来技術に対し、出願人は予てよりＣｕ電極
材及びＭｏやＷに代わる新しい熱膨張整合材どして、Ｃ
ｕとインバー（Ｆｅ −３６，５％Ｎｉ合金）のクラッ
ト材の開発を検討してきた。その結果、Ｃｕとインバー
のクラツド材ではその構成によっては熱膨張整合性を兼
ね備えた電極材として非當に有用であることが確認され
た。In response to such conventional technology, the applicant has been developing Cu electrode materials and new thermal expansion matching materials to replace Mo and W.
We have been considering the development of a crat material of U and Invar (Fe-36,5%Ni alloy). As a result, it was confirmed that Cu and Invar cladding materials are extremely useful as electrode materials that have thermal expansion matching, depending on their configuration.
本発明の目的は、かかるクラツド材の改良として、熱放
散性・電気伝導性・熱膨張整合性・半ｌ１１１付性に総
合的に優れた半導体支持電極用クラッド祠を提供するこ
とにある。An object of the present invention is to provide, as an improvement of such cladding materials, a cladding for semiconductor supporting electrodes that is comprehensively superior in heat dissipation, electrical conductivity, thermal expansion matching, and semi-I111 adhesion.
すなわち本発明の要旨は、インバー板の両面に銅板を配
置しこれらを積層一体化したクラツド材からなるものに
おいて、前記インバー板の体積比率をクラット材全体の
２０〜８０％としたことがある。That is, the gist of the present invention is that the material is made of a clad material in which copper plates are arranged on both sides of an Invar plate and these are laminated and integrated, and the volume ratio of the Invar plate is 20 to 80% of the entire clad material.
インバーは周知のように優れた低熱膨張係数（１，２＞
（１０−６／”Ｃ）を有する合金であり、しかもＣｕな
どと同じように一般材わ１として豊富であると共に軟か
く加工しやすい特徴を有している。As is well known, Invar has an excellent low coefficient of thermal expansion (1,2>
(10-6/''C), and like Cu, it is abundant as a general material and has the characteristics of being soft and easy to process.
第１図はインバー板ｌの両面にＣｕ板２，２を配置し、
これら冷間圧延により圧接一体化したクラツド材３の断
面構造を示す。第２図はこのようなりラッド材３におい
て、インバー板ｌの板厚を変えることによりその体積比
率を変えた場合の板面に平行方行の熱膨張係数αと、熱
伝導重大の変化をみたものである。つぎにこの第２図作
成に用いたクラット材３を電極材として第４図のような
半導体装置を組立て、これにより実際の実負荷試験を行
った。この結果、このようなりラット材からなる電極材
としては、インバーの体積比率が２０％未満ではυ１膨
張係数がＣｕの値に近づきすぎ半導１体素子との熱膨張
整合性に問題があり、またインバーの体積比率が８０％
を越ると実装状態において熱放散性の面で不十分である
ことが認められた。なお、かかる限定、範囲は飽くまで
もインバー板の両面に銅板を配置した３層構造のクラッ
ト材からなるものの場合であり、クラット材の構造が異
なればその限定範囲も自ずと異なってくるものと思われ
る。さらに本発明のクラット材は、銅板が外側表面に位
置されたことにより、特に熱放散性・電気 伝導性・半
田付性に優れているものである。In Figure 1, Cu plates 2, 2 are placed on both sides of the Invar plate l,
The cross-sectional structure of the clad material 3 which has been pressure-welded and integrated by cold rolling is shown. Figure 2 shows the changes in the thermal expansion coefficient α parallel to the plate surface and the significant changes in heat conduction when the volume ratio is changed by changing the thickness of the invar plate l in Rud material 3. It is something. Next, a semiconductor device as shown in FIG. 4 was assembled using the crut material 3 used in the preparation of FIG. 2 as an electrode material, and an actual load test was conducted using this device. As a result, when the volume ratio of Invar is less than 20% for an electrode material made of such a rat material, the υ1 expansion coefficient is too close to the value of Cu, and there is a problem in thermal expansion compatibility with the semiconductor monolithic element. Also, the volume ratio of Invar is 80%
It was found that when the temperature exceeds 1000 nm, the heat dissipation performance is insufficient in the mounted state. Note that these limitations and ranges are strictly for the case of a three-layered crat material with copper plates arranged on both sides of an invar board, and it is thought that the range of limitations will naturally differ if the structure of the crat material differs. Furthermore, the crat material of the present invention has particularly excellent heat dissipation, electrical conductivity, and solderability because the copper plate is placed on the outer surface.
第４図は本発明の一実施（り゛）に係る半導体装置の構
造を示す。この半導体装置は第１図に示されるＣｕとイ
ンバーの３ｒＦＡ構造のクラツド材３を電極材４とし、
この上に直接シリコンを半田（ｔ Ｌ、たものである。FIG. 4 shows the structure of a semiconductor device according to one embodiment of the present invention. This semiconductor device uses a 3rFA structure cladding material 3 of Cu and invar shown in FIG. 1 as an electrode material 4,
Silicon was soldered directly onto this.
なお、６は半田付部・７はアルミナ絶縁体・８はＣｕ支
持板である。In addition, 6 is a soldering part, 7 is an alumina insulator, and 8 is a Cu support plate.
このほかに前記クラツド材の半導体装置への適用例とし
ては、サイリスタやパワートランジスタなどへの応用が
ある。Other applications of the cladding material to semiconductor devices include thyristors, power transistors, and the like.
さて第４図の半導体装置において、実負荷状態において
熱■υ張性のはかζご注目しなければならないことばυ
１放散性であり、この場合シリコン５から発生する熱を
いかに放熱させ、そして各構成材を通してＣｕ支持板（
ヒートシンク）８に伝えるかであるが、熱伝導率で比較
し！ご場合、従来のＭＯは約帆３５ｃａｌ ／ｃｍ−ｓ
ｅｃ −’Ｃであるが、本クラット材３てはインバーの
体積１．ヒ率が８０％で約帆０３Ｃａ１／Ｃｍ１ＳｅＣ
１℃てあリインバーの体積比率が２０％で約０．１．５
ｃａｌ ／ｃｍ ” ｓｅｃ ・℃とＭＯと比較して小
さい値であることから、熱放散性の面で心配がある。し
かしながら本クラツド材によれば、銅板を外側に配置し
た構成とすることにより、半導体装置実負荷時の温度分
布解析例（図示せず）をみるとわかるように、板面方向
への熱拡がりが太きいために全体の熱抵抗はＭＯの場合
と大差がない。Now, in the semiconductor device shown in Figure 4, there are some words that we must pay attention to: thermal υ tensile properties υ under actual load conditions.
In this case, how to dissipate the heat generated from the silicon 5, and how to dissipate the heat generated from the silicon 5 through the Cu support plate (
Heat sink) 8, but let's compare it by thermal conductivity! In your case, the conventional MO is approximately 35 cal/cm-s
ec -'C, but the volume of invar in this crat material 3 is 1. When the hit rate is 80%, it is about 03Ca1/Cm1SeC
At 1℃, the volume ratio of Reinvar is 20% and it is approximately 0.1.5.
Since this is a small value compared to cal/cm sec ・°C and MO, there is concern about heat dissipation.However, according to this clad material, by having a configuration in which the copper plate is placed on the outside, As can be seen from an example of temperature distribution analysis (not shown) when a semiconductor device is actually loaded, the overall thermal resistance is not much different from that of MO because the heat spreads widely in the direction of the plate surface.
したがって本クラット材は十分ＭＯの代替として使用で
きることが確認された。なお、この点については次の試
験によっても認めることができる。Therefore, it was confirmed that this crat material can be used as a sufficient substitute for MO. This point can also be confirmed by the following test.
第５図および第６図は本クラツド材をパワートランジス
タの電極材として応用した場合の温度（Ｊイクルの試験
結果を示す。温度サイクルは、いずれも１５（１℃（２
５分）→室温（５）→−５５°Ｃ（２５分）→室温（５
分）という条件で行なわれた。Figures 5 and 6 show test results of temperature (J cycle) when this cladding material is applied as an electrode material of a power transistor.
5 minutes) → Room temperature (5) → -55°C (25 minutes) → Room temperature (5
It was carried out under the following conditions:
第７１４および第８図は本クラツド材をパワートランジ
スタの電極材として応用した場合のパワーサイクル試験
結果を示す。パワーサイクル試験は５０°Ｃ〜８０℃の
間で行なわれた。Figures 714 and 8 show the results of a power cycle test when the present cladding material was applied as an electrode material for a power transistor. Power cycling tests were conducted between 50°C and 80°C.
第５〜８図をみるとわかるように、いずれの試験におい
ても熱抵抗が非常に安定しており、木クラット材は熱放
散性の面で実用上問題のないことが確認された。As can be seen from Figures 5 to 8, the thermal resistance was very stable in all tests, and it was confirmed that the wood crat material had no practical problems in terms of heat dissipation.
以」−のように本発明の半導体支持電極用クラット材に
よれば、インバー板の両面に銅板を配置した構成のクラ
ツド材において、インバー板の体積比率を全体の２０〜
８０％としたことにより、熱膨張整合性を兼ね備えた電
極材として良好な熱放散性・電気伝導性・半田付性を示
すと共に熱抵抗が非常に安定しているために従来のＭｏ
やＷに代わる新しい材料として使用することができる。As described below, according to the cladding material for semiconductor supporting electrodes of the present invention, in the cladding material having a structure in which copper plates are arranged on both sides of the invar plate, the volume ratio of the invar plate is 20 to 20% of the total.
80%, it exhibits good heat dissipation, electrical conductivity, and solderability as an electrode material with thermal expansion matching, and has extremely stable thermal resistance, making it superior to conventional Mo.
It can be used as a new material in place of or W.
また、本クラツド材を使用することにより半導体装置の
コストダウン、小型化を大幅に前進させることが可能と
なり、その工業的価値はきわめて大きいものがある。Furthermore, by using this cladding material, it is possible to significantly reduce the cost and size of semiconductor devices, and the industrial value thereof is extremely large.
第１図はＣｕ／インバー／ Ｃｕクラット材の断面図、
第２図はインバーの体積比率に関係する特性図、第３図
は従来の半導体装置の構造を示す部分断面図、第４図は
本発明の一実施例に係る半導体装置の構造を示す部分断
面図、第５図及び第６図は夫々温度サイクル試験結果を
示す説明図、第７図及び第８図は夫々パワーサイクル試
験結果を示す説明図である。
１：インバー板、２：銅板、３：クラット材。
０ ２（１４０６０８０＋ｏ。
イノｌ＼−のイ本＃、よヒ率（九）
Ｎ３図 第 ４０
６′
斥 ｓ５
見 ′ｒ図
ハ＠７−サイフル数 （回）
宛 ８ 図
１マフ−サイ２ル数 （回り
第１頁の続き
０発 明 者 大高達也
土浦市木田余町３５５０番地日立電
線株式会社金属研究所内Figure 1 is a cross-sectional view of Cu/Invar/Cu crat material.
FIG. 2 is a characteristic diagram related to the volume ratio of Invar, FIG. 3 is a partial sectional view showing the structure of a conventional semiconductor device, and FIG. 4 is a partial sectional view showing the structure of a semiconductor device according to an embodiment of the present invention. 5 and 6 are explanatory views showing the results of the temperature cycle test, respectively, and FIGS. 7 and 8 are explanatory views showing the results of the power cycle test, respectively. 1: Invar plate, 2: Copper plate, 3: Krat material. 0 2 (1406080+o. Ino l\-'s book #, Yohi rate (9) N3 figure No. 40 6' Rejection s5 See 'r figure Ha@7- Saiful number (times) To 8 Figure 1 Muff-Sai 2 le Number (Continued from page 1) Inventor: Tatsuya Otaka, Hitachi Cable, Ltd., Metals Research Laboratory, 3550 Kidayocho, Tsuchiura City
Claims (1)
一体化したクラツド材からなるものにおいて、前記イン
バー板の体積比率をクラツド材全体の２０〜８０％とし
たことを特徴とする半導体支持電極用クラッド材。(1) A semiconductor support electrode made of a clad material in which copper plates are arranged on both sides of an Invar plate and these are laminated and integrated, wherein the volume ratio of the Invar plate is 20 to 80% of the entire clad material. cladding material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58123649A JPS6015937A (en) | 1983-07-07 | 1983-07-07 | Cladding material for semiconductor support electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58123649A JPS6015937A (en) | 1983-07-07 | 1983-07-07 | Cladding material for semiconductor support electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6015937A true JPS6015937A (en) | 1985-01-26 |
Family
ID=14865822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58123649A Pending JPS6015937A (en) | 1983-07-07 | 1983-07-07 | Cladding material for semiconductor support electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6015937A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04184964A (en) * | 1990-11-20 | 1992-07-01 | Toshiba Corp | Aluminium nitride package |
| US5506447A (en) * | 1993-06-15 | 1996-04-09 | Fuji Electric Co., Ltd. | Hybrid integrated circuit |
| WO2004105141A1 (en) * | 2003-05-22 | 2004-12-02 | Neomax Materials Co., Ltd. | Electrode wire material and solar battery having connection lead formed of the wire material |
| WO2005114751A1 (en) | 2004-05-21 | 2005-12-01 | Neomax Materials Co., Ltd. | Electrode wire for solar battery |
| JP2006245153A (en) * | 2005-03-02 | 2006-09-14 | Neomax Material:Kk | Electrode connecting wire material for solar cell, and solar cell connected with wire material |
| JP2019114651A (en) * | 2017-12-22 | 2019-07-11 | 晶呈科技股▲分▼有限公司 | Structure of vertical light-emitting diode die and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5842243A (en) * | 1981-09-07 | 1983-03-11 | Hitachi Cable Ltd | Supporting electrode plate for semiconductor element |
-
1983
- 1983-07-07 JP JP58123649A patent/JPS6015937A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5842243A (en) * | 1981-09-07 | 1983-03-11 | Hitachi Cable Ltd | Supporting electrode plate for semiconductor element |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04184964A (en) * | 1990-11-20 | 1992-07-01 | Toshiba Corp | Aluminium nitride package |
| US5506447A (en) * | 1993-06-15 | 1996-04-09 | Fuji Electric Co., Ltd. | Hybrid integrated circuit |
| WO2004105141A1 (en) * | 2003-05-22 | 2004-12-02 | Neomax Materials Co., Ltd. | Electrode wire material and solar battery having connection lead formed of the wire material |
| WO2005114751A1 (en) | 2004-05-21 | 2005-12-01 | Neomax Materials Co., Ltd. | Electrode wire for solar battery |
| US7754973B2 (en) | 2004-05-21 | 2010-07-13 | Neomax Materials Co., Ltd. | Electrode wire for solar cell |
| EP3012872A2 (en) | 2004-05-21 | 2016-04-27 | Hitachi Metals, Ltd. | Solar cell |
| JP2006245153A (en) * | 2005-03-02 | 2006-09-14 | Neomax Material:Kk | Electrode connecting wire material for solar cell, and solar cell connected with wire material |
| JP4683466B2 (en) * | 2005-03-02 | 2011-05-18 | 株式会社Ｎｅｏｍａｘマテリアル | Electrode connection wire for solar cell and solar cell connected by the wire |
| JP2019114651A (en) * | 2017-12-22 | 2019-07-11 | 晶呈科技股▲分▼有限公司 | Structure of vertical light-emitting diode die and manufacturing method thereof |
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