JPS60154671A - Semiconductor device - Google Patents

Abstract

PURPOSE:To integrate MOSFETs having short gate length and large gate width in high density by forming a current flowing passage between the source and the drain of the MOSFET on the side substantially perpendicular to the surface of a substrate. CONSTITUTION:An n type epitaxial layer 210 is grown on the entire substrate, a silicon oxide film 41, a silicon nitride film 42 and a silicon oxide film 43 are accumulated, patterned and selectively etched. Then, with the films 41-43 as masks the layer 210 is etched selectively substantially perpendicularly. Thereafter, a silicon oxide film 25 is formed by thermally oxidizing on the entire surface. Subsequently, a silicon nitride film is accumulated on the entire surface, and the silicon nitride film 44 remains only on the side of a projection by dry etching. Thereafter, with the film 44 as a mask a silicon oxide film 27 is formed by thermally oxidizing. After the film 44 is then removed, a polycrystalline silicon 24 is accumulated on the overall surface. Then, a polycrystalline silicon on the silicon single crystal projection is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the manufacture and construction of semiconductor devices, and in particular to the field of isolation suitable for very small integrated circuits with very high speed and very low power performance. Goo 1 ~ Type electric field transistor (
[Background of the Invention] FIG. 1 shows a cross-sectional view of the structure of a conventional MOSFET. The conventional n-channel MO5FET has a p-type substrate 1
1, source and drain 11 type diffusion regions 12.1
3 is formed, and has a structure in which a gate electrode 14 is formed on a gate oxide film 15. Note that 1G is a selectively formed silicon oxide film for element isolation. The conventional MOSFET shown in FIG. 1 has the following drawbacks because the current conduction path between the source and drain is provided on a surface horizontal to the substrate.

(1) The source and drain electrodes have holes (contact holes) smaller than the source and drain diffusion regions 12.13.
hole). Therefore, the source/drain diffusion region has at least contacts 1 to 1.
The parasitic capacitance between this diffusion region and the substrate 1 cannot be ignored. The charging and discharging time of this parasitic capacitance slows down the switching operation of the device.

(2) The gate capacitance and electron transit time, which determine the operating speed of the device, are proportional to the gate length. Therefore, it is necessary to shorten the gate length for high-speed operation. Since the gate length is determined by phosphorography, it is difficult to shorten it.

(3) In order to quickly charge and discharge the load capacitance of the next stage, it is necessary to increase the gate width and increase the mutual conductance. This results in an increase in the area of the device in proportion to the gate width.

(4) Since the current conduction path is on the substrate surface, it is susceptible to radiation such as alpha rays. This reduces the reliability of a circuit using the same element.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks and provide a semiconductor device with high density, high speed, and low power consumption.

[Summary of the invention]

In order to achieve the above object, the present invention has a configuration in which a current conduction path between the source and drain is provided by a substantially vertical side wall of a semiconductor single crystal. The current flowing through the current conductive path is controlled by a voltage applied to a polycrystalline silicon layer provided through a thin oxide.

This polycrystalline silicon layer is insulated from the semiconductor substrate by a thick oxide film.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a plan view of a first MO5FET type semiconductor device as an embodiment of the present invention, and FIG.
' shows a cross-sectional view of the structure.

In FIG. 3, reference numeral 23 denotes a highly doped n-type drain diffusion layer provided on the surface of the p-type substrate 21. P shadow area 211,
The high-concentration n-shaded regions 22 and 28 are formed by sequentially adding impurities to the n-type epitaxial layer 2 and O on the substrate, and in particular, 22 represents a source diffusion layer. A silicon oxide film 25 and a gate electrode 24 are provided in contact with the substantially vertical sidewalls of the P shadow region 211 .

The gate electrode 24 is insulated from the substrate 21 and the high concentration n-swelled diffusion layer region 23 by silicon oxide films 26 and 27.

FIG. 4 shows the manufacturing process of the first semiconductor device of the present invention, and shows the state before the cross-sectional structure of FIG. 3 is obtained.

The manufacturing process will be explained below according to the drawing numbers.

FIG. 4(a): Impurities are selectively added to the surface of the p-type silicon substrate 21 to form a high concentration n-type layer region 23. FIG. Thereafter, an n-type epitaxial layer 210 is grown on the entire surface of the substrate, and a silicon oxide film 41, a silicon nitride film 42, and a silicon oxide film 43 are deposited and patterned to form a three-layer film 4.
Selective etching from 1 to 43.

FIG. 4(b): Using the three-layer films 41 to 43 as a mask, the epitaxial layer 210 is selectively etched almost vertically (5). Thereafter, a silicon film (7) and an oxide film (25) are formed on the entire surface by thermal oxidation.

Figure 4 (C): A silicon nitride film is deposited on the entire surface, and then dry etched to form a silicon nitride film 4 only on the side surfaces of the protrusions.
Leave 4. Thereafter, a silicon oxide film 27 is formed by thermal oxidation using the silicon nitride film 44 as a mask.

FIG. 4(d): After removing the silicon nitride film 44, polycrystalline silicon 24 is deposited on the entire surface.

FIG. 4(e): After removing the polycrystalline silicon on the silicon single crystal convex portion, a silicon nitride film is deposited on the entire surface and patterned to leave a portion 45 of the silicon nitride film. Thereafter, a portion of the polycrystalline silicon 24 is thermally oxidized using the silicon nitride film 45 as a mask to form a silicon oxide film 26.

FIG. 4(f) After adding impurities to the region from which the Ni-Drain electrode will be taken out to form a highly concentrated black region 28, the silicon nitride film 45 and the silicon oxide film 43 are gradually removed. Thereafter, the surface of the polycrystalline silicon 24 is oxidized using the silicon nitride film 42 as a mask. After that, P-type impurities and N-type impurities are sequentially added from the surface to form the P shadow region 211.
The structure shown in FIG. 3 is obtained by forming a high concentration n shadow region 22, and forming a gate/contact hole 29 and aluminum electrode wiring.

FIG. 5 shows a second MOS F as another embodiment of the present invention.
FIG. 6 is a plan view of the E'II semiconductor device, and FIG. 6 is a structural sectional view taken along the line V-V' in FIG.

In this example, an oxide film 25 is formed on the side surface of a portion of the epitaxial layer 210 on the gate 1, and a polycrystalline silicon layer 24(b) is directly connected to the side surface of the other portion of the epitaxial layer 210. This is done by selectively etching a part of the oxide film 25 by patterning after removing the silicon nitride film 44 in FIG. This is achieved by Fifth. In FIG. 6, 51 is polycrystalline silicon 24 (b
) is a P shadow region formed by diffusion of p-type impurities contained in the epitaxial layer 210 into the epitaxial layer 210. The P shadow region 211 is electrically connected to the P shadow region 51 and connected to the aluminum electrode through the polycrystalline silicon layer 24 (b) and the contact hole 29 (b), and by applying a voltage thereto, the threshold of the MOSFET can be adjusted. Voltage can be controlled.

FIG. 7 shows a third MO3FET as another embodiment of the present invention.
1 is a cross-sectional structural diagram of a shaped semiconductor device. In this example, an n-type epitaxial layer 210 is in contact with a p-type substrate 21. Furthermore, in the manufacturing process diagram FIG. 4(b), by adding P-type impurities to the entire surface, the P shadow region 7 in FIG.
1 is formed.

The P shadow region 211 is electrically connected to the P type substrate 21 through the P shadow regions 51 and 71, and by applying a voltage to the substrate, the thread shoulder voltage of the MOS F IE'r can be controlled. The example in this figure is p shadow area 2.
Since the wiring for the voltage applied to 11 is done by the board,
This has the advantage that the element area is smaller than the elements shown in FIGS. 5 and 6. Note that in FIG. 7, 24(b) and 51 may be omitted. However, in that case, the P shadow areas 71 and 211 must be connected.

In each of the following Embodiments 1 to 3, the insulator may be formed by thermal oxidation of silicon, or an insulating resin or the like may be used in addition to a silicon nitride film.

Furthermore, the conductivity types of P type and +1 type can be used in reverse. Furthermore, the source and drain can also be used in reverse. The device of the present invention can also be realized using other semiconductors such as GaAs as the semiconductor.

〔Effect of the invention〕

According to the present invention, the current conduction path between the source and drain of the MOSFET is formed on the substantially perpendicular side surface of the substrate surface, making it possible to integrate MO3 FIETs with short goo lengths and large gate widths at high density. Furthermore, since parasitic capacitance is reduced, it is possible to realize MO3Fi7T with high speed and low power consumption. Furthermore, the probability that radiation such as α-rays will irradiate the source-drain current conduction path is reduced, and MO5, which is resistant to this radiation,
F[ET can be realized.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional structure diagram of a conventional MOS V El'', Fig. 2 is a plan view of a MOSFET as an embodiment of the present invention, and Fig. 3 is a cross-sectional structure taken along line I-II' in Fig. 2. figure,
FIGS. 4(a) to 4(f) show the manufacturing method of the semiconductor device of the present invention. 5 is a plan view of MO3FET' as another embodiment of the present invention, FIG. 6 is a sectional structural diagram taken along v-v' in FIG. 5, and FIG. FIG. 3 is a cross-sectional structure diagram of a MOSFET as still another example. 21...p-type substrate, 23...high concentration Tll region 2
10... N type epitaxial region, 211... P shadow region, 22.28... High concentration II type region 25... Gate oxide film, 26.27... Silicon oxide film, 24...
...Polycrystalline silicon, 29...Gate contact 1~
Hole, 51...No 1 Figure 1Ii Z z Figure 3 Figure 4 (λ) (C) Figure 4 (Note 9 (e) Figure 5 Continued from page 1 of Figure 10 Inventor Takahiro Okabe Kokubunji City Higashi Koigakubo Research Institute

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, and a first conductivity type of a second conductivity type opposite to the first conductivity type provided on the surface region of the substrate.
an insulator provided on the base surface and having an opening over at least a portion of the first region; and a second region of the IJL crystal semiconductor layer provided over the opening.
a third region of a polycrystalline semiconductor layer provided on the second region of the insulating film and in contact with at least a part of the substantially vertical sidewall of the second region with an insulating material in between; A semiconductor device comprising: a fourth region of a first conductivity type provided within the fourth region; and a fifth region of a second conductivity type provided within the fourth region.