JPS60138962A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable to form ohmic contacts with favorable wirings by a method wherein each barrier layer of a high-melting point metal silicide is selectively formed in contact windows provided in n type semiconductor regions (each inclusive of both of a single crystal region and a polycrystalline region), and after that, metal wirings are performed. CONSTITUTION:A p type source region 3 and a p type drain region 4 are formed in a region surrounded with the field oxide films 2 of an n type silicon single crystal substrate 1, while a big p type well 5 is formed in another region surrounded with one of the field oxide films 2 and another field oxide film 2 and an n type source region 6 and an n type drain region 7 are formed. A molybdenum layer 11 is ashered on the whole surface, a resist 12 is applied thereon, and apertures are respectively provided selectively on the n type source region 6, the n type drain region 7 and gate electrodes 9 of polycrystalline silicon by performing a patterning. After a condition that a reaction of molybdenum and silicon is easy to generate has been brought by ion-implanting arsenic, an annealing is performed and barrier layers 13 are respectively formed on the n type source region 6, the n type drain region 7 and the gate electrodes 9. Aluminum layers (each an alloy containing silicon of 1%) 14 are respectively adhered on the p type drain region 3, the p type drain region 4, the n type source region 6, the n type drain region 7 and the gate electrodes 9, and metal wirings (electrodes) are formed by performing a patterning.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, particularly C-M
OS (Complementary Metal
Oxide Semiconductor) type semiconductor device'#i. This relates to a method of forming poles.

Prior Art and Problems C-MO8 integrated circuits (ICs) are being actively developed because they have the advantages of low power consumption, power, and high speed. However, there are problems with C-MO8 ICLv% and pole formation. In a C-MOS IC, for example, a p-type source region and a drain region are formed in an n-type single crystal silicon substrate, and a polysilicon gate electrode is formed on a channel region between them with a gate oxide film interposed therebetween. , a large p-type well is formed in the substrate, an n-type source region and a drain region are formed therein, and a polysilicon gate electrode is formed on the channel region between them with a gate oxide film interposed therebetween. There is. Toshita C-MOSIC p
When wiring is formed with aluminum (for example, 1T silicon alloy) for the expansion diffusion layer region, the n-type diffusion layer region, and the polysilicon region, a p-type epitaxial layer doped with aluminum is formed within the contact window. For,
Good electrical contact and ohmic contact are not achieved in the n-swelled diffusion layer region and the polysilicon region,
This tendency is particularly noticeable when the contact window is small.

Purpose of the Invention In view of the current state of the prior art as described above, the present invention is directed to C-MO
The purpose of this invention is to form ohmic contacts with good wiring to p-type and n-type silicon regions (including BOLIN 1) in an S-type semiconductor device.

Structure of the Invention In order to achieve the above object, the present invention selectively forms a barrier layer of a high melting point metal silicide within a contact window of an n-type semiconductor region (including both a single crystal region and a polycrystalline region). Then do the metal wiring. In the p-type scattering layer region, it is possible to make direct contact with the metal (AI-8i) ohmic, and even in the n-shade region, if the above barrier layer exists, it is good (resistance is low and stable). Ohmic contact is achievable. Since high-melting point metal silicide does not form good ohmic contact with the p-shade region, it is necessary to form it selectively in the n-shade region. However, selective formation of a refractory metal silicide layer is not easy, and using simple selective etching or simple lift-off increases alignment, making the process increasingly complex. Therefore, in the present invention, impurities are selectively implanted into the high melting point metal layer formed on the entire surface of the substrate with the bond window opened, and then annealing is performed to convert the relevant portion into 7 silicide, and the remaining portions that have not been silicided are removed. Remove the melting point metal layer.

Embodiment of the Invention An embodiment in which the present invention is applied to a C-MOS transistor will be described. Referring to FIG. 1, a p-type source region 3 and a p-type drain region 4 (each boron-doped , I
x 10"cm-2) is formed, and a large p-type well (
Boron-doped, 5X1013 cm-2) is formed in which an n-type source region and a bent drain region 7 are formed.
(Arsenic tone respectively.

4X1 r)"cm-2) is formed. Also, 1,
Gate electrodes 9 made of polysilicon (phosphorous doped, 15'/gj) are formed on the seven-type and n-type channels, respectively, with a gate acid film 8 interposed therebetween. all over).

Although covered with a PEG film 10, electrode windows are formed in each source and drain region 3, 4, 6.7 and the oxide film and PEG film 10 directly on the gate electrode 9. i
: Referring to FIG. 2, the molybdenum layer 11 has a thickness of 5.
Approximately 0III11 adheres. A resist layer of about 1 .mu.m thick is applied thereon and patterned to selectively open holes on the nm-thick source region 6 and drain region 7 and on the polysilicon gate electrode 9.

Accelerating arsenic at a voltage of 70 keV and a dose of 4 x 10
By implanting ions at a depth of about 15 cm-2, the reaction between molybdenum and silicon in the ion-implanted region is facilitated. When annealing is performed at 550° C. for 30 minutes in a nitrogen atmosphere, the n-type source region 6, n-type drain region 7 and A barrier layer 13 of molybdenum silicide (Mo8i2) is formed within the contact window of the gate electrode 9.

The residue of the molybdenum layer 11 that has not been silicided can be selectively removed with aqua regia.

After removing the resist 12, the resist 105 is removed using a halogen lamp.
Flash annealing f is performed at 0° C. for about 10 seconds. This makes the barrier layer 13 completely silicided.

Referring to FIG. 3, an aluminum layer (1% silicon alloy) 14 is deposited and patterned to form wiring (electrodes). Next, annealing is performed at 450° C. for about 30 minutes to compensate for electrical (ohmic) contact with aluminum in the p shadow region. In this way, p shadow region 3
, 4, aluminum and silicon form good electrical (ohmic) contact directly, and in n-shaded regions 6, 7 and polysilicon region 9, good electrical contact is made between aluminum and silicon through a barrier layer of molybdenum silicide. is formed.

In addition to molybdenum silicide, tungsten silicide, tantalum silicide, titanium silicide, etc. can also be used as the barrier layer.

Any impurity implanted to promote silicidation may be used as long as it does not adversely affect device characteristics.

Effects of the Invention As is clear from the above explanation, according to the present invention, C-M
Layout (t+
, poles) can be achieved.

[Brief explanation of drawings]

FIGS. 1 to 3 are cross-sectional views of a semiconductor device in the order of steps to explain the present invention in detail. l...n-type silicon substrate, 2...field oxide film. 3...p-type source region, 4...p-type drain region,
5...-p-type well, 6... n-type source region, 7...
・P-type drain region, 9... Gate electrode (polysilicon), 11... Molybdenum layer, 13... Barrier layer (
molybdenum silicide), 14... wiring (aluminum). Patent applicant Fujitsu Limited Patent application agent Akira Kanki Patent attorney Kazuyuki Nishidate Patent attorney Yukio Uchida Patent attorney Akiyuki Yamaguchi

Claims (1)

[Claims] 1. Aluminum □ Lamb metal connected directly and via a high-melting point gold silicide layer to each of the p-type region and the n-conductivity type region formed in the semiconductor substrate. A semiconductor device characterized in that a geometries/tufts are formed by an electrode wiring layer. :2.Exposed through an opening formed in the surface insulating film: Exposed p-1 type region and n, -conductivity type region □. A high melting point metal layer 11 is formed on the entire surface of the silicon semiconductor substrate, and a position I is formed on the n-conductivity type region of the high melting point metal layer.
By selectively injecting impurities into the part where f is ′:
・). , 1 on the n-conductivity type region by annealing from
Selectively generate high melting point metal silicide within the opening.
[The remainder of the high melting point metal layer that is not silicided]
□:・,: is removed and a metal wiring layer is formed to make p-conductor 11
, j-type region and n-conducting tRL-type region, respectively.
1.1 A method for manufacturing a semiconductor device characterized by making contact metals.