JPS60134433A - Inspection for semiconductor wafer - Google Patents

Abstract

PURPOSE:To shorten the test time for wafers by a method wherein, when numerous chips are formed on each wafer by the same process and the chip characteristics of each of the chips are inspected in the state of wafer, firstly, a sampling inspection is carried out in every (n) pieces and when a defective was defected from among the (n) pieces of chips, (m) pieces of chips are successively tested, because the (m) pieces of chips in the vicinity of the chip detected as a defective and the defective chip extremely resemble each other in chip characteristics. CONSTITUTION:A signal generating circuit 1 is used for inspecting the chip characteristics of chips having been formed on a wafer. A devide-by-(n) counter 2, which counts the number of (n) pieces of chips for making a sampling inspection in every (n) pieces, and a divide-by-(m) counter 3, which counts the number of (m) pieces of chips for successively inspecting (m) pieces of chips when a defective was detected, are provided in the circuit 1. Here, it is desirable that the relation between the (m) and the (n) is m>n. Then, AND gates G1, G2 and G3 and OR gates OR1, OR2 and OR3 are provided between the counters 2 and 3. Firstly, an inspection is carried out by the counter 2, and when a defective was detected, chips in the vicinity of the chip detected as a defective are inspected by the counter 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor chip inspection method performed during the manufacturing process of a semiconductor device, and particularly relates to an improvement of an inspection method performed in a wet state. Technology> LS1. In the process of manufacturing semiconductor devices such as ICs, various performance tests are carried out during the process in order to improve production efficiency. As a result of advances in finer wiring and higher integration, the inspection process in the manufacturing process of integrated circuit devices, which takes half a day off work, has significantly increased the time required for inspection. This is now taking up a considerable amount of time and has become the biggest bottleneck.

The inspection processes currently being carried out in the LSI manufacturing process can be roughly divided into the W/T (wafer test) process, which is carried out on each chip in the wafer state, and the test process, which is carried out on the final product after all processes have been completed. F/T (Final test)
The inspection time can be divided into two steps, and the increase in inspection time affects both of them. Therefore, in order to shorten the inspection time, in the W/T process, due to the nature of the process, there is no need for very strict inspection, so all inspection items are not inspected, and the yield of the F/T process is reduced. It has been proposed to conduct inspections that do not cause excessive deterioration, and this has also been adopted in actual processes. In other words, the inspection time is shortened by omitting inspection items.

The important point here is that the inspection items that can be omitted in the W/T process are only those with a low failure rate.

In addition, even if the defect rate is normally low, there may be cases where the defect rate suddenly increases due to changes in the ever-processing process. It is not preferable to omit .

<Object of the Invention> The present invention has been made in view of the problems with the conventional inspection methods described above, and can prevent a decrease in yield in the F/T process while shortening the inspection time in the W/T process. This is an inspection method.

<Example> The figure shows an inspection apparatus l for carrying out the inspection method according to the present invention.
FIG. 2 is a block diagram of a circuit that generates a chip extraction signal of FIG. The signal generating circuit 1 performs a sampling inspection every nth chip on a wafer that is sequentially sent.
An n-ary counter 2 is provided to count the number of defects, and an m-ary counter 3 is provided to count the number of m items that must be continuously inspected when a defect is detected. Here, it is desirable to design fm>n. A first AND gate G1 is provided at the input terminal of the n-ary counter 2, and the inspection request input signal 4 and the overflow signal 5 of the m-ary counter 3 are applied to the input terminal of the first AND gate G1. There is.

The inverted signal 5 of the overflow signal 5 output from the m-ary counter 3 is inputted together with the inspection request input signal 4 to the second AND gate G2 provided at the input stage of the m-ary counter 3. The second AND gate G2. The output of is applied to the m-adic counter 3 and also to the first OR gate OR1 to form the inspection request output signal 6. That is, the first
At the other input terminal of the OR gate OR, an inspection request output signal 6 for a sampling inspection is formed by a signal from the second AND gate G2 of the n-ary counter 2.

The overflow signal 7 of the n-ary counter 2 is applied to the reset terminal of the n-ary counter 2, and when it counts n items, it resets its own counter. An inverted signal 7 of the overflow signal 7 is applied to the third antagonist G3. The output signal of the first AND gate G1 is applied to the other input terminal of the third AND gate G3.
The output of No. 3 is a test completion input signal 8 outputted from the tester for each test item to the second input terminal, and a test completion output signal 9 is output from the second OR gate OR2 to perform the test for the input test request item. Indicates that the process has ended.

Corresponding to the completion of the above inspection, a signal indicating whether the test result is good or bad is output from the tester, but the good product input signal 10 is outputted as the good product output signal ll via the third OR gate OR3, and the defective product The input signal 12 is output as a defective product output signal 3. The defective product input signal 12
is also applied to the reset terminal of the m-ary counter 3, and when a defective product is detected, the m-ary counter 8 is reset, and the inspection request output signal 6 is continuously sent to the subsequently sent m chips. form.

The operation of the inspection device having the above configuration will be explained.

If inspection in the W/T process is completely omitted, there is a risk that the F/T yield will decline at some point due to changes in the wafer process, etc. In the example, changes in the wafer process are monitored by inspecting every n pieces. The setting of IInI+ that should not be subjected to sampling inspection is determined empirically depending on the number of chips produced per wafer and the probability of producing good products and defective products.

Every time n inspection request input signals 4 are counted, an overflow signal 7 output from the n-ary counter 2 generates an inspection request output signal 6 via the first OR gate G1, and a sampling inspection is performed. When a change in the wafer process or a change in wafer characteristics is detected by sampling every n chips, that is, when a defective input signal 12 occurs, the lη-adic counter 3 is reset and the number of chips to be tested after that is n chips. The inspection request input signal 4, which is issued every time each chip is sent, is used to conduct m-measurements through the second AND gate G2 and the first OR gate G1 until the m-adic counter 3 overflows. It is arbitrarily set depending on the number of sheets, etc. When the above m consecutive tests are completed, I
The second AND gate G2 is cut off by the overflow signal of the n-ary counter 8, and the inspection request signal 4 is inputted to the n-ary counter 2 every n items again through the first AND gate G1ff, thereby performing a sampling inspection every n items. Return to

In the above inspection process, if the wafer or the same lot is the same, the wafer or the lot has similar characteristics and is sampled and measured, and if a defect is detected,
Since inspections are performed continuously on the sea urchins or lots, the F/T yield may decrease somewhat compared to the case where 100% is inspected from the beginning, but it is considered to reduce the number of man-hours in the W/T process. And the benefits are great.

The above inspection method can be partially applied only to test items with a low incidence of small insects in a process with a high W/T yield such as IC.

<Effects> According to the present invention, since a large number of chips are mounted on a wafer that has gone through the same process, sampling is performed every n chips for inspection, and if a defect is detected, the characteristics of neighboring chips are changed. By continuously testing m pieces because they are extremely similar, it is possible to shorten the test time or test man-hours for wafer testing while preventing a drop in final test yield due to sudden changes in the wafer process. be able to.

[Brief explanation of drawings]

The figure is a block diagram of a chip extraction signal generation circuit for explaining one embodiment of the present invention. 2: N-ary counter, 3: M-ary counter, 4: Inspection request input signal, 6: Inspection request output signal, 8: Inspection end input signal, 9: Inspection request output signal, 10: Good product input signal, 12:
Defective product input signal, 61~G3: AND gate, OR, ~
0R3 Nioa Gate.

Claims (1)

[Claims] l) In the process of inspecting chip characteristics in a wafer state, a test chip is extracted every n chips on the wafer,
Execute the inspection items on the extracted test chips to form a non-defective signal or a defective product signal, and with the above-mentioned non-defective signal formed, continue extracting the test chips for every n chips until the defective product signal is detected. A method for inspecting a semiconductor wafer, characterized in that a single chip following a test chip in a formed state is continuously used as a test chip.