JPS60100245A - Address converter - Google Patents

Abstract

PURPOSE:To reduce the number of bits per datum by having access by address to which virtual address register contents as well as ID register contents, which an address signal reading out a head address of segment table, are linked. CONSTITUTION:While converting a virtual address into an actual address, eight bits of 8-15 of a virtual address register 1 are made into LA at a prescribed address within an address conversion buffer 14, and 13 bits of a read-out real page address are made into RA to write them respectively, and set a flag V to a logic 1. When the device is set to the register 1, the converter reads out the buffer 14 by making five bits of 15-20 of said register into a lower address and by making three bits of the ID register 9 into an upper address. The converter compares eight bits within data 15 with 8-15 of the register 1, and the converter sets the register to 8-20 of a real address register 7 at their coincidence, thereby eliminating an ID bit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an address translation device in a data processing device employing a virtual memory method.

[Prior art]

Since the virtual storage system is well known, a general explanation thereof will be omitted. However, virtual addresses are used in software, and this virtual address is used in an address conversion device, and the l: storage address is converted to the storage address in Figure 1. 1 is a block diagram showing an example of a conventional address translation device, and (1) is a virtual address register in which a virtual address is set. Numbers 8, 15 outside the block of virtual address register (1)
, 16 , 20 , 21 .

31 indicates the focus number. In all figures below, numbers outside the blocks of all registers (or memories) indicate bit symbols. (2) is the starting address of the segment table (Segment 'I"able
The STO register (hereinafter abbreviated as STO) can be set, (3) is the segment table, +41rJ: the start address of the page table (Page Table O
(hereinafter abbreviated as PTO), (5) is a page table, (6) is a real page address, and (7) is an H real address register.

The entire storage area is divided into multiple segments, each segment of the multiple segments is divided into multiple pages, and one segment containing the multiple pages is usually 1
It is called a space. When multiple user programs are executed in parallel in a time-sharing manner, one space is allocated to each user program, and when one user program is being executed, one space is allocated to that user program. STO indicating space is set in the STO register (2), and a virtual address is set in the virtual address register (1).

Conversion from a virtual address to a real address is performed as follows. Virtual address register (1) 8-15 8
The bit is segment intex and the STO register (2
) and add this segment index to the address and output the segment table (3), P
TO (41 is read. Virtual address register (1)
The 5 bits from 16 to 20 are the page index and PTO
If the page table +51'k is read using the value obtained by adding this page intex to f41 as an address, the real page address (6) is read.

Since the IT bits 21 to 31 of the virtual address register (1) are composed of the lower 11 bits of the real address and 161-, these are stored as 21 to 31 of the real address register (7):
(Set as 11 bits of J, real page address (6 bits)
) of 8 to 20 of real address register (7).
If the address is 13 bits, the 24-bit virtual address from 8 to 31 is converted to a real address from 8 to 31,024 bits and set in the real address (4) address register (7).

If each virtual address is converted into a real address using the method described above each time, the disadvantage is that it takes a lot of processing time because the segment table (:tsu) and page table (5) have to be read each time. be.

In general, 21 to 31 of virtual address register (1)
Even if the 11 bits of He are changed, 8 to 20013 bits are often the same bit pattern in succession, and once the real page address (6) corresponding to this bit pattern has been generated, this Usually, the address is stored in an address translation buffer and then read from this buffer to perform address translation at high speed.

FIG. 2 is a block diagram showing a conventional device using an address translation buffer. The same reference numerals as in FIG. The numbers on the left indicate the address. In the example shown in the figure, eight types of STO are stored in the scratchpad memory (
5cratchpad memory) is set to the following address. For example, if the content of the register (9) is roloJ, this indicates that the STO at address 2 of the STO stack (8) is the currently executed STO.

In the UOrri address translation buffer, Table Lo
The following TLB means okasideBuffer.
It is abbreviated as Ql) Indicates one data of HTLB contents L
A U 8-bit virtual address bits (corresponding to 8 bits 8 to 15 of virtual address register il+),
RA is 13 bits of real page address bits (corresponding to bits 8 to 20 of real address register (7)), ID
ID bit corresponding to 3 bits of Ltll) register (9), V is LA.

This is a 1-bit flag indicating whether or not recording of RA and ID is valid. TLB 111 stores 32 data shown in (11), and virtual address register (1)
16 to 2005 bits (page index). 0.2 and Q3 are each comparators.

When the real page address of the virtual address register II + 77') 1 bit V'&l 18', 7-IQ bit is pushed out by the method described in connection with FIG. (
1) 5 bits 16 to 2o are the address, and 8 to 5 bits are the address.
8-pit ff: 13-bit real page address read in the LA area; current ID in the RA area;
Write the contents of register (9) to each eID column,
The flag V is set to logic "1". However, the above-mentioned writing is executed only when the desired conversion data does not exist in TLB o, tJ in the following explanation.

Next, address translation operation using TLB +It3 will be explained. The virtual address is the virtual address register f
When accessed to i+, the 5 bits 16 to 2o are used as an address to obtain TLB DOt-read data αη.

LAi virtual address register (1 of data (1ll)
) with 8 bits 8 to 15 using a comparator (c),
Of the data 0υ, the content of the ID pit eID register is compared with the comparator 0:4, and if both the comparators +t'a and o3 indicate a match and the flag V is logic "1" (this case is assumed to be TLB ( 10 was a hit), the RA of data aη is a real page address, so if this is set as the 13 pits 8 to 20 of the real address register, it will be converted to a real address and killed.

If TLB (Lf3) is not hit, it is sufficient to write to TLB (10) using the method explained earlier.

By the way, in general, there are other types of STOs than the eight types stored in the 5TI-jsTO stack (8), and if you need an STO that does not exist in the STO stack (8), the STO stack (8) ) has existed for a long time.
One of the STOs must be erased and a new required STO must be written into the STO stack (8), but at that time, the contents of the TLB (10) related to the erased STO must be indicated as invalid. To do this, set the address in the STO stack (8) of the erased STO in the ID register, change the address of TLB (It) *r+v<, and indicate a match from the comparator (13). When the signal is output, the flag (2) of the data is set to logic "0".

Since the conventional device is configured as described above, (I
Since the ID pinot) is inserted into the TLB Qf) data, the number of bits in the data is often large.

(Comparator α3 is required to compare the IID bits.

(c) When the contents of the STO stack (8) are epicentered, the operation of erasing the data valid flag of TLB (1 (j) (hereinafter referred to as TLB partial purge) is complicated.

) TLB +l (j has a small number of data (32 in the above example), so the hit rate of 'I'LB is low.

[Summary of the invention]

This invention was made in order to eliminate the hot spots of the conventional ones as described above, and in this invention, each STO has 32
(If the STO has 8af types, the number of data in the TLB will be 256 data), and the ID
By accessing the 'ILB using an 8-bit address concatenated with 3 bits of bits and 5 bits of the page index, the ID bit is removed from the data in the TLB, thus removing comparator f11, and removing the STO stack ( The data that should be invalidated when changing the contents of 8) is TLB.
Since the upper address (3 bits) of 32 consecutive data are in the same location, it is easy to invalidate it, and the TL
Since the number of H data is increased, the hit rate can be improved.

[Embodiments of the invention]

Embodiments of this invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.
The same reference numerals as in the figure indicate the same or equivalent parts, and u41 is one data in the rLB, αυij TLB Q4 of the present invention.

As explained with reference to FIG. 2, if TI, [41 is not hit, the 13 bit e of the real page address corresponding to the 13 bits 8 to 2o of the virtual address register is Read out. The correspondence between the read real page address and the virtual address is written to the TLB (10) as follows. That is, the 3 bits of the ID register (9) are set as the upper 3 bits, and the 16th to 2nd bits of the virtual address register (1) are written. Using the 8-bit address concatenated with the 5 bits of the address as the lower address, use the TLB specified by the address (virtual address register at address 11 (8 to 1508 pits of 11 as LA, 13 bits of the read real page address) write as RA,
Set flag V to logic "1".

If the TLBO saving has been completed and the virtual address is set in the virtual address register +11, these 6 to 2
005 bit is the lower address, ID register (9)
TBL (14kit
The LA bit 8 bits of the read data θυ are compared with the virtual address register (11 8 bits to 15 bits 8 bits) by comparator 0, and it is determined that the two match, and
If the flag V is logic 1-1, the relevant data (RA bit 15 is a real page address, so set it as bits 8 to 20 of the real address register (7), and set it as bits 8 to 20 of the virtual address register + 11). 11 bits 21 to 31 are set to 21 to 30 of the real address register (7).
Setting this bit completes the translation from a virtual address to a real address.

In addition, in the device shown in Fig. 3, in order to store a new s'ro 1 in the s'ro stack (8), the previously existing ST
If you want to evict the STO at a specific address among O, set that specific address in the ID register (9), and
By ignoring the lower 5 bits of the address of LB Q41 and sequentially writing logic "0" to all the ■ flags for the 32 data corresponding to the upper 3 bits of the address given from register +91, good.

In addition, in the above example, for convenience of explanation, the number of bits in each field of each Jli register is assumed to be a value of QM 7, and the STO guy of the s'ro stack (8), T
The explanation has been given assuming a specific numerical value for the number of data in L Ba<, but the present invention applies the limiting expression 21. to such a numerical example. Needless to say, this is not something that can be done.

〔Effect of the invention〕

As described above, according to the present invention, step 1) Since the contents of the register and the contents of some bits of the virtual address register are concatenated to form the TLB address, the ID bit is smaller than that of the conventional TLB. This reduces the bit length per data, making comparators for more bits unnecessary, and increasing
The process for partial purge B could be simplified.

By increasing the number of TLB data, it is possible to improve the hit rate of 'rL1.The increase in cost for increasing the number of TLB data is due to
(random access, memory)
Due to recent advances in technology, it has become possible to supply it at a low cost, so it is not a problem.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional address translation device, FIG. 2 is a block diagram showing an example of a conventional device using an address translation buffer, and FIG. 3 is a block diagram showing an embodiment of the present invention. It is. +11...Virtual address register, (K...Real address register, (8)...STO stack, (9)...
...ID register, a2... comparator, (1...T
LB, Qυ...Data in TLB. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masu Oiwa Ha1 Figure 1 c531 8 31 Supplementary procedure IE t'i' (self-motivated) Showa: i! J.71.6:3. Relationship with the case of the person making the amendment Patent applicant address: 2-2-3 Kunouchi, Chiyo FJI-ku, Tokyo
Name (601,) Mitsubishi Electric Co., Ltd. Representative: Katayuni Hachibe 4, Agent address: 2-2-3 Kuunouchi, Chiyo F11-ku, Tokyo (1)
1BA Specification, "Detailed Description of the Invention" column], Contents of the amendment (1) Page 3 of the specification, lines 14 to 17, it says, "The whole...of multiple types.""Multipletypes"
I am corrected. (2) Specification page 11, line 6 rTBLJ and r
Correct as TLB J. (that's all)

Claims (1)

[Scope of Claim] An address translation device that converts a virtual address into a real address using an address translation buffer includes an 8TO stack that stores the start address of a segment table in each space, and a start address of a desired segment table from this STO stack. ID from which the address signal for reading the entire address is to be sectored
The virtual address register in which the rear address is set, and the page index of the contents of this virtual address register as the lower address, and the above I1) by the address concatenated with the contents of the register as the upper address. means for accessing an address translation buffer; a comparator for comparing a virtual address bit of the output data with a segment index of the contents of the virtual address register; a comparison result of the comparator indicates a match, and and means for setting a real page address bit of the read data as an upper bit of a real address register when a valid flag of the read data indicates validity. conversion device.