JPS60106178A - Gate circuit of compound semiconductor element - Google Patents
Gate circuit of compound semiconductor elementInfo
- Publication number
- JPS60106178A JPS60106178A JP21460283A JP21460283A JPS60106178A JP S60106178 A JPS60106178 A JP S60106178A JP 21460283 A JP21460283 A JP 21460283A JP 21460283 A JP21460283 A JP 21460283A JP S60106178 A JPS60106178 A JP S60106178A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- circuit
- voltage
- compound semiconductor
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 150000001875 compounds Chemical class 0.000 title claims description 13
- 230000006698 induction Effects 0.000 claims description 6
- 230000003068 static effect Effects 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 4
- 239000003990 capacitor Substances 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
本発明は、ＧａＡＳ等の化合物半導体を用いた静電誘導
型トランジスタ（ＳＩＴ）や接合型ＦＥＴＬＪＦＥＴ）
を駆動するゲート回路に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a static induction transistor (SIT) or a junction type FETL (JFET) using a compound semiconductor such as GaAS.
This invention relates to a gate circuit that drives a gate circuit.
［発明の技術的背景とその問題点］
５１−Ｍ０８ＦＥＴは中電力用の高速スイッヂング素子
として近年著しく発展してきたが、１０００■以上の高
耐圧素子はオン抵抗が大きすぎるという欠点がある。こ
れは、オン抵抗Ｒｏｎが耐圧ｖｂの約２．５乗に比例す
ることによる。これに対して、ＧａＡＳを用いると、電
子の移動度がＳｉのそれに比べてはるかに大きいため、
低損失で高速の素子が得られる可能性がある。ところが
ＧａＡＳでは、ＭＯＳＦＥＴの製造は困難であるため、
ショットキー・ゲート構造またはｐｎ接合ゲート構造が
利用される。[Technical background of the invention and its problems] Although the 51-M08FET has developed significantly in recent years as a high-speed switching element for medium power use, a high breakdown voltage element of 1000 Å or more has the drawback that its on-resistance is too large. This is because the on-resistance Ron is proportional to about the 2.5th power of the breakdown voltage vb. On the other hand, when GaAS is used, the electron mobility is much higher than that of Si, so
It is possible to obtain a high-speed device with low loss. However, since it is difficult to manufacture MOSFETs using GaAS,
A Schottky gate structure or a pn junction gate structure is utilized.
Ｇ ａ Ａ Ｓのｐｎ接合ゲート構造を用いた電力用ス
イッチング素子としては、ＳＩＴあるいはＪＦＥＴが知
られている。第１図はＳＩＴの基本構造を示している。SIT or JFET is known as a power switching element using a GaAs pn junction gate structure. FIG. 1 shows the basic structure of SIT.
１は高濃度ｎ型ドレイン層、２は低濃度ｎ型層、３は高
濃度ｐ型ゲート層、４は高濃度ｎ型ソース層であり、格
子状にうめこまれたグー１〜層３に囲まれた領域がチャ
ネル領域５となっている。この素子には、ゲート・ソー
ス間バイアス電圧ＶＱが零の時にチャネル領域が空乏層
で満たされているノーマリ・オフ型と、ＶＱが零で電流
が流れるノーマリ・オン型とがある。図はｎチャネル素
子を示している。1 is a highly doped n-type drain layer, 2 is a lightly doped n-type layer, 3 is a heavily doped p-type gate layer, and 4 is a heavily doped n-type source layer, which are surrounded by layers 1 to 3 of goo embedded in a lattice pattern. The lowered region becomes the channel region 5. There are two types of this device: a normally-off type in which the channel region is filled with a depletion layer when the gate-source bias voltage VQ is zero, and a normally-on type in which current flows when VQ is zero. The figure shows an n-channel device.
この様なＳＩＴは、通常、ゲート電流を流さない高イン
ピーダンス状態で電圧制御によるユニポーラ型の動作を
さＩるが、正のＶＱを印加すると素子のオン抵抗が低下
し、ＶＱの増大に伴って素子はユニポーラ型の動作から
バイポーラ型の動作に移行する。このうちバイポーラ型
の動作では二つのモードが区別される。このことを第２
図を参照しながら詳しく説明する。This kind of SIT normally operates in a unipolar type by voltage control in a high impedance state where no gate current flows, but when a positive VQ is applied, the on-resistance of the device decreases, and as VQ increases, The device transitions from unipolar to bipolar operation. Among these, two modes are distinguished in bipolar operation. This is the second
This will be explained in detail with reference to the figures.
ゲート・ソース間電圧ＶＧが正の小さい値の間はゲート
電流を流すことなくチャネル領域５に伸びていた空乏層
を縮小させて素子のオン抵抗を小さくすることができる
。ｖｑが大きくなるにつれ、チャネル領域５の少数キャ
リアの蓄積が多くなってくる。蓄積する少数キャリアの
濃度ｎは次の式％式％
）
このキャリア濃度が低濃度ｎ型層２の濃度を越えると導
電変調が起り、オン抵抗Ｒｏｎは著しく低下するように
なる。いまｎ型層２の１度を４×１４３
０／ｃｍとすると、この境界はおよそＶＯ＝Ｏ。While the gate-source voltage VG is at a small positive value, the depletion layer extending into the channel region 5 can be reduced without flowing a gate current, and the on-resistance of the device can be reduced. As vq increases, more minority carriers accumulate in the channel region 5. The concentration n of accumulated minority carriers is determined by the following formula (%) (%) When this carrier concentration exceeds the concentration of the low concentration n-type layer 2, conductivity modulation occurs and the on-resistance Ron significantly decreases. Now, assuming that 1 degree of the n-type layer 2 is 4×1430/cm, this boundary is approximately VO=O.
９Ｖとなる。従ってＶｑが０．９Ｖを越えるど矢チャネ
ル領域を含めたｎ型層２が導電変調を受けてＲＯｎが低
下するが、更にＶｇが高くなってゲート・ソース間のビ
ルトイン電圧を越えるとゲート層３を含む全面がオンす
るバイポーラトランジスタ動作をするようになる。It becomes 9V. Therefore, the n-type layer 2 including the channel region where Vq exceeds 0.9V undergoes conductivity modulation and ROn decreases, but if Vg further increases and exceeds the built-in voltage between the gate and source, the gate layer 3 It operates as a bipolar transistor in which the entire surface including the transistor is turned on.
このようなバイポーラトランジスタ動作領域に入ると、
直流電流増幅率ｔ−＋ｒｅに相当するドレイン電流Ｉｄ
とゲート電流ＩＣ＋の比Ｉｄ／Ｉｃ＋の値が極端に小さ
くなってくる。またドレイン電流密度□Ｊｄも１０３Ａ
／Ｃｄを越えてしまう。更にこの動作モードでは素子を
ターンオフしようとすると多くの蓄積キャリアをゲート
から吸出す必要があるが、ゲートの抵抗が高い場合には
素子内部に電圧降下を生じ、素子を一様にターンオフで
きず電流集中を起こし、これが素子破壊の原因となる。When entering such a bipolar transistor operating region,
Drain current Id corresponding to DC current amplification factor t-+re
Then, the value of the ratio Id/Ic+ of gate current IC+ becomes extremely small. Also, the drain current density □Jd is 103A
/Cd will be exceeded. Furthermore, in this mode of operation, in order to turn off the device, it is necessary to suck out many accumulated carriers from the gate, but if the gate resistance is high, a voltage drop occurs inside the device, and the device cannot be turned off uniformly, causing a current drop. Concentration occurs, which causes element destruction.
［発明の目的］
本発明は、ＧａＡＳ等の化合物半導体を用いたＳＩＴや
ＪＦＥＴを、前述した深いバイポーラトランジスタ動作
を避けて安全に制御して高速動作させるゲート回路を提
供することを目的とする。[Object of the Invention] An object of the present invention is to provide a gate circuit that safely controls and operates a SIT or JFET using a compound semiconductor such as GaAS at high speed while avoiding the deep bipolar transistor operation described above.
［発明の概要］
本発明は、ＧａＡＳ等のＳＩＴまたはＪＦＥＥＴのゲー
ト・ソース間にバイアスを与えるゲート回路内に、ゲー
ト・ソース間順方向バイアス電圧を制限するクランプ回
路を設けたことを特徴とする。[Summary of the Invention] The present invention is characterized in that a clamp circuit that limits the forward bias voltage between the gate and source is provided in the gate circuit that applies bias between the gate and source of SIT or JFEET such as GaAS. .
このクランプ回路は、例えばツェナーダイオードにより
構成すればよく、クランプ電圧はゲート・ソース間のビ
ルトイン電圧を越えないように設定すればよい。This clamp circuit may be constructed of, for example, a Zener diode, and the clamp voltage may be set so as not to exceed the built-in voltage between the gate and the source.
［発明の効果］
本発明によれば、化合物半導体を用いたＳＩＴやＪＦＥ
Ｔのゲート・ソース間に順方向バイアスをあたえて低い
オン抵抗Ｒｏｎを得る場合にも、深いバイポーラトラン
ジスタ動作を避けて素子破壊を確実に防止することがで
きる。[Effects of the Invention] According to the present invention, SIT and JFE using compound semiconductors
Even when applying a forward bias between the gate and source of T to obtain a low on-resistance Ron, deep bipolar transistor operation can be avoided and element destruction can be reliably prevented.
［発明の実施例］ 第３図は本発明の一実施例の等価回路である。[Embodiments of the invention] FIG. 3 is an equivalent circuit of one embodiment of the present invention.
図において、１１は主電源、１２は負荷、１３はノーマ
リ・オン型のｎチャネルＧａＡｓ−８ＩＴである。ゲー
ト回路１４は、正のゲート電源１５゜負のゲート電１１
６．これらの電源を切替えてゲートに供給するスイッチ
１８．および二つのツェナーダイオード１７−１と１７
−２を逆方向に直列接続したクランプ回路により構成し
ている。ツェナーダイオード１７−１．１７−２はＧａ
Ａｓを用いて５ＩＴ−１３と一体的に形成されている。In the figure, 11 is a main power supply, 12 is a load, and 13 is a normally-on type n-channel GaAs-8IT. The gate circuit 14 has a positive gate power supply 15 degrees and a negative gate power supply 11.
6. A switch 18 that switches these power supplies and supplies them to the gate. and two Zener diodes 17-1 and 17
-2 are connected in series in opposite directions. Zener diode 17-1.17-2 is Ga
It is formed integrally with 5IT-13 using As.
その降伏電圧は５ＩＴ−１３のゲート・ソース間ビルト
イン電圧とほぼ等しく設定されている。Its breakdown voltage is set approximately equal to the gate-source built-in voltage of 5IT-13.
このような構成において、５ＩＴ−１３に正のゲート電
源１５を与えてバイポーラ型の動作をさせる場合、高速
のスイッチング動作をさせるにはこのゲート電源１５の
電圧値を大きくしてゲート電流の立上がりを速くする必
要がある。本実施例では、このゲート電源１５の電圧値
を十分大きくしても、５ＩＴ−１３のゲート・ソース間
に印加される電圧はそのビルトイン電圧を越えることが
ない。従って高速のスイッチング動作が可能でしかもキ
ャリアの異常な蓄積を防止して安全な動作が行われる。In such a configuration, when applying the positive gate power supply 15 to the 5IT-13 to perform bipolar operation, in order to perform high-speed switching operation, the voltage value of the gate power supply 15 must be increased to suppress the rise of the gate current. Need to be fast. In this embodiment, even if the voltage value of this gate power supply 15 is made sufficiently large, the voltage applied between the gate and source of 5IT-13 will not exceed its built-in voltage. Therefore, high-speed switching operation is possible, and safe operation is performed by preventing abnormal accumulation of carriers.
第４図は本発明の別の実施例の等価回路である。FIG. 4 is an equivalent circuit of another embodiment of the present invention.
この実施例は５ＩＴ−１３がｎチャネルのノーマリ・オ
フ型の場合である。従ってゲート回路１４は、正のゲー
ト電源１５と、これを選択的にゲートに供給するスイッ
チと、一つのツェナーダイオード１７からなるクランプ
回路とから構成している。ツェナーダイオード１７はや
はり５ＩＴ−１３のビルトイン電圧とほぼ等しい降伏電
圧を有し、５ＩＴ−１３と一体形成されている。In this embodiment, 5IT-13 is an n-channel normally off type. Therefore, the gate circuit 14 includes a positive gate power supply 15, a switch that selectively supplies the positive gate power supply to the gate, and a clamp circuit consisting of one Zener diode 17. Zener diode 17 also has a breakdown voltage approximately equal to the built-in voltage of 5IT-13, and is integrally formed with 5IT-13.
この実施例によっても、クランプ回路を設けている結果
、５ＩＴ−１３を破壊することなく高速動作させること
ができる。Also in this embodiment, since the clamp circuit is provided, the 5IT-13 can be operated at high speed without being destroyed.
第５図は更に別の実施例を示す等価回路である。FIG. 5 is an equivalent circuit showing yet another embodiment.
この実施例も５ＩＴ−１３はｎチャネルのノーマリ・オ
フ型であるが、先の実施例と異なり二つの正のゲート電
源１５−１．１５−２を有する。電源１５−１は５ＩＴ
−１３のゲート電流の立上がりを十分速くするための高
電圧電源であり、電源１５−２は５ＩＴ−１３のビルト
イン電圧とほぼ等しく設定された低電圧電源である。高
電圧電源１５−２の出力はダイオード１９を介して抵抗
２０とコンデンサ２１からなる積分回路に接続されてい
る。そしてこのコンデンサｚ１の出力と低電圧電源１４
の出力が逆流素子ダイオード２２．２３を介し、スイッ
チ１８を介して同時に５ＩＴ−１３のゲートに供給され
るようになっている。クランプ回路として、５ＩＴ−１
３ど一体形成されたＧａＡＳツェナーダイオード１５を
有することは先の実施例と同じである。The 5IT-13 in this embodiment is also an n-channel normally off type, but unlike the previous embodiment, it has two positive gate power supplies 15-1 and 15-2. Power supply 15-1 is 5IT
The power supply 15-2 is a high voltage power supply for making the rise of the gate current of -13 sufficiently fast, and the power supply 15-2 is a low voltage power supply set almost equal to the built-in voltage of 5IT-13. The output of the high voltage power supply 15-2 is connected via a diode 19 to an integrating circuit consisting of a resistor 20 and a capacitor 21. And the output of this capacitor z1 and the low voltage power supply 14
The output of the 5IT-13 is simultaneously supplied to the gate of the 5IT-13 via the reverse current element diodes 22 and 23 and the switch 18. 5IT-1 as a clamp circuit
This embodiment is the same as the previous embodiment in that it has three integrally formed GaAS Zener diodes 15.
この実施例によれば、先の実施例と同様の効果が得られ
る他、次のような効果も得られる。即ちこの実施例では
スイッチ１８が閉じるとコンデンサ２１の電荷が急激に
放電され速いゲート電流の立上がりで５ＩＴ−１３をタ
ーンオンさせるが、ターンオン後のゲート電圧は低電圧
電源１５−２から主として供給される。このためツェナ
ーダイオード１７が電圧をクランプする期間はコンデン
サ２１が放電する間だけであり、ツェナーダイオードに
過大な電流が流れない。つまり高電圧電源１５−１を用
いて速いゲート電流の立上がりを得ているが、ツェナー
ダイオード１７として小容量のものを用いることができ
る。According to this embodiment, in addition to the effects similar to those of the previous embodiment, the following effects can also be obtained. That is, in this embodiment, when the switch 18 is closed, the charge in the capacitor 21 is rapidly discharged, and the 5IT-13 is turned on by the rapid rise of the gate current, but the gate voltage after turning on is mainly supplied from the low voltage power supply 15-2. . Therefore, the period during which the Zener diode 17 clamps the voltage is only while the capacitor 21 is discharging, and no excessive current flows through the Zener diode. That is, although the high voltage power supply 15-1 is used to obtain a fast gate current rise, a Zener diode 17 with a small capacity can be used.
本発明は上記実施例に限られない。上記実施例では専ら
ＳＩＴを用いたが、ＧａＡＳ−ＪＦＥＴにも同様に本発
明を適用することができる。またＧａＡＳに限らず他の
化合物半導体を用いた８１ＴやＪＦＥＴにも本発明を適
用出来るし、クランプ回路はこれらの素子と一体形成さ
れていなくてもよい。The present invention is not limited to the above embodiments. Although SIT was exclusively used in the above embodiment, the present invention can be similarly applied to GaAS-JFET. Further, the present invention can be applied not only to GaAS but also to 81T and JFET using other compound semiconductors, and the clamp circuit does not have to be integrally formed with these elements.
第１図はＳＩＴの基本構成を示す図、第２図はその動作
モードを説明するための図、第３図は本発明の一実施例
の等価回路を示す図、第４図および第５図は他の実施例
の等価回路を示す図である。
１１・・・主電源、１２・・・負荷、１３・・・ＱａＡ
ｓ−８ＩＴ、１４・・・ゲート回路、１５．１５−１．
１５−２．１６・・・ゲート電源、１７．１７−１．１
７−２・・・ＧａＡｓツェナーダイオード（クランプ回
路）、１８・・・スイッチ。
出願人代理人 弁理士 鈴江武彦FIG. 1 is a diagram showing the basic configuration of SIT, FIG. 2 is a diagram for explaining its operation mode, FIG. 3 is a diagram showing an equivalent circuit of an embodiment of the present invention, and FIGS. 4 and 5 FIG. 3 is a diagram showing an equivalent circuit of another embodiment. 11... Main power supply, 12... Load, 13... QaA
s-8IT, 14... gate circuit, 15.15-1.
15-2.16...Gate power supply, 17.17-1.1
7-2...GaAs Zener diode (clamp circuit), 18...Switch. Applicant's agent Patent attorney Takehiko Suzue
Claims (6)
ランジスタまたは接合型ＦＥＴのグー１〜・ソース間に
バイアスを与えるゲート回路において、前記ゲート・ソ
ース間の順方向バイアス電圧を制限するクランプ回路を
設けたことを特徴とする化合物半導体素子のゲート回路
。(1) In a gate circuit that applies a bias between the gate and source of a static induction transistor or junction FET constructed using a compound semiconductor, a clamp circuit that limits the forward bias voltage between the gate and the source. A gate circuit for a compound semiconductor device, characterized in that it is provided with:
り構成したものである特許請求の範囲第１項記載の化合
物半導体素子のゲート回路。(2) A gate circuit for a compound semiconductor device according to claim 1, wherein the clamp circuit is constituted by a Zener diode.
のビルトイン電圧を越えないクランプ電圧を有するもの
である特許請求の範囲第１項記載の化合物半導体素子の
クランプ回路。 （３） 前記クランプ回路は、前記静電誘導型１〜ラン
ジスタまたは接合型ＦＥＴ内に一体的に形成されたもの
である特許請求の範囲第１項記載の化合物半導体素子の
ゲート回路。(3) The clamp circuit for a compound semiconductor device according to claim 1, wherein the clamp circuit has a clamp voltage that does not exceed a built-in voltage between the gate and the source. (3) The gate circuit for a compound semiconductor device according to claim 1, wherein the clamp circuit is integrally formed within the electrostatic induction transistor or junction FET.
Ｔはノーマリ・オン型であり、前記ゲート回路は、正及
び負のゲート電源とこれを切替えてゲートに供給するス
イッチを有する特許請求の範囲第１項記載の化合物半導
体素子のゲート回路。(4) The electrostatic induction transistor or junction FE
2. The gate circuit for a compound semiconductor device according to claim 1, wherein T is a normally-on type, and the gate circuit has a positive and negative gate power supply and a switch for switching between the positive and negative gate power supplies and supplying the power to the gate.
Ｔはノーマリ・オフ型であり、前記ゲート回路は、グー
［・・ソース間に順方向バイアスを与えるゲート電源と
これをゲートに供給するスイッチを有する特許請求の範
囲第１項記載の化合物半導体素子のゲート回路。(5) The electrostatic induction transistor or junction FE
The compound semiconductor device according to claim 1, wherein T is of a normally-off type, and the gate circuit has a gate power source that applies a forward bias between the sources and a switch that supplies this to the gate. gate circuit.
Ｔはノーマリ・オフ型であり、前記ゲート回路は、積分
回路とスイッチを介してゲートに供給される。グー１〜
・ソース間に順方向バイアスを与える高電圧グー１〜電
源と、この電源と同極性で上記スイッチを介して直接ゲ
ートに供給される低電圧ゲート電源とを逆流素子ダイオ
ードを介して併設して構成したものである特許請求の範
囲第１項記載の化合物半導体素子のゲート回路。(6) The electrostatic induction transistor or junction FE
T is a normally-off type, and the gate circuit is supplied to the gate via an integrating circuit and a switch. Goo 1~
- Consisting of a high-voltage power source that provides forward bias between the sources and a low-voltage gate power source that has the same polarity as this power source and is directly supplied to the gate via the above switch via a reverse current element diode. A gate circuit for a compound semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21460283A JPS60106178A (en) | 1983-11-15 | 1983-11-15 | Gate circuit of compound semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21460283A JPS60106178A (en) | 1983-11-15 | 1983-11-15 | Gate circuit of compound semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60106178A true JPS60106178A (en) | 1985-06-11 |
Family
ID=16658426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21460283A Pending JPS60106178A (en) | 1983-11-15 | 1983-11-15 | Gate circuit of compound semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60106178A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1989005041A1 (en) * | 1987-11-23 | 1989-06-01 | Hughes Aircraft Company | Zener diode emulation and method of forming the same |
| WO2022074196A1 (en) * | 2020-10-08 | 2022-04-14 | Danfoss Silicon Power Gmbh | Power electronic module comprising a gate-source control unit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5591155A (en) * | 1978-12-27 | 1980-07-10 | Toshiba Corp | Semiconductor integrated circuit device |
-
1983
- 1983-11-15 JP JP21460283A patent/JPS60106178A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5591155A (en) * | 1978-12-27 | 1980-07-10 | Toshiba Corp | Semiconductor integrated circuit device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1989005041A1 (en) * | 1987-11-23 | 1989-06-01 | Hughes Aircraft Company | Zener diode emulation and method of forming the same |
| US4910158A (en) * | 1987-11-23 | 1990-03-20 | Hughes Aircraft Company | Zener diode emulation and method of forming the same |
| WO2022074196A1 (en) * | 2020-10-08 | 2022-04-14 | Danfoss Silicon Power Gmbh | Power electronic module comprising a gate-source control unit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5550701A (en) | Power MOSFET with overcurrent and over-temperature protection and control circuit decoupled from body diode | |
| US9660551B2 (en) | Operating point optimization with double-base-contact bidirectional bipolar junction transistor circuits, methods, and systems | |
| Shekar et al. | Characteristics of the emitter-switched thyristor | |
| JPH02126677A (en) | Semiconductor device | |
| US20170345917A1 (en) | Electric assembly including a bipolar switching device and a wide bandgap transistor | |
| JPH0564889B2 (en) | ||
| Shekar et al. | High-voltage current saturation in emitter switched thyristors | |
| Shimizu et al. | Controllability of switching speed and loss for SiC JFET/Si MOSFET cascode with external gate resistor | |
| JPH0449266B2 (en) | ||
| US5665988A (en) | Conductivity-modulation semiconductor | |
| EP0177513B1 (en) | Integrated circuit and method for biasing an epitaxial layer | |
| US6674107B1 (en) | Enhancement mode junction field effect transistor with low on resistance | |
| JPS60106178A (en) | Gate circuit of compound semiconductor element | |
| JP3655049B2 (en) | Driving method of electrostatic induction transistor | |
| US3931632A (en) | Switching device equipped with a semiconductor memory element | |
| JP6879572B2 (en) | Operation of a double-based bipolar transistor with additional timing phase during switching transients | |
| Veliadis | 1200 V SiC vertical‐channel‐JFETs and cascode switches | |
| JPH04364784A (en) | Mos type semiconductor element driving circuit | |
| WO1991017570A1 (en) | Insulated gate bipolar transistor | |
| Biswas et al. | An autoprotecting gate drive circuit for GTO thyristors | |
| JP2818611B2 (en) | Semiconductor relay circuit | |
| JPS61161015A (en) | Composite semiconductor switching device | |
| JPS59225A (en) | Bidirectional controlling circuit | |
| JPS59103425A (en) | Switching device | |
| JP3115716B2 (en) | Semiconductor device |