JPS648933B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a pulse counting method that improves errors caused by flicker prevention circuits. [Prior art] When the difference between the latest counted value and the displayed value is less than a predetermined value, the displayed value is held, and when it exceeds the predetermined value, the latest counted value is updated and displayed as the displayed value, and the latest counted value is set as the predetermined value. A pulse counting method is known that updates and displays the latest counted value as a display value when the minimum display unit continues to change a predetermined number of times. Figure 1 shows a block diagram of this pulse counting method. Pulse signals input from input terminal 1 are counted by counter 2, and when counting is completed, counter 2
The counted value of is stored in the register 3, and the counted value of the counter 2 and the register 3 are added in the adder 4 during the gate time period, this added value is updated and held in the latch circuit 5, and displayed via the decoder driver 6. It is digitally displayed on device 7. Further, the difference between the latest count value added by the adder 4 and the display value of the latch circuit 5 is determined by the digital comparator 8, and the difference is a predetermined value (in this example, the display unit is "1"). , the comparator 8 outputs a signal to the counters 9 and 9' depending on whether the value is positive or negative, and the number of times this signal continues is counted. When, comparator 1
A load pulse is output from 0 and the OR gate 11
The content of the latch circuit 5 is updated to the latest count value via the latch circuit 5, and the change is digitally displayed on the display 7. In addition, in this conventional example, the gate time is divided into two,
When changes within a predetermined value occur three times in a row in the same positive and negative directions, the displayed value shall be updated to the latest counted value, and in order to absorb fluctuations in the minimum display unit (1 km/h), the predetermined value shall be changed. The value corresponds to the minimum display unit. [Problems to be Solved by the Invention] However, in the conventional pulse counting method configured in this way, even when input pulses are stably input at a constant frequency, depending on whether the frequency is decreasing or increasing, The disadvantage was that the displayed values were different. Generally, changes in the input frequency of less than the display unit (1 km/h) are counted by the counter 2 and added by the adder 4.
The number of pulses added in the gate period only increases and decreases periodically, and the displayed value is displayed in units of 1 Km/h by rounding up or down. In other words, at an input frequency of 1 Km/h such as 1 Km/h, 2 Km/h, etc., the number of pulses in the gate period only increases or decreases by 1 pulse, but if the change is less than 1 Km/h, The number of pulses does not change uniformly in the gate period, but changes in the number of pulses in multiple periods. For example, at 2.5Km/h, 5
This is the number of pulses, and the input frequency is equivalent to 2.5 pulses in one gate period, and at 2.45 km/h, which is slightly lower than 2.5 km/h, the number of pulses is 49 pulses in 20 gate periods. Also, at 2.55Km/h, which is slightly higher than 2.5Km/h, the number of pulses is 51 pulses in 20 gate periods, and 50 pulses in 20 gate periods at 2.5Km/h.
It can be seen that a change in pulse rate of 0.05 Km/h results in an increase or decrease of one pulse in 20 gate periods. The above change in the number of pulses causes a periodic increase/decrease in the number of pulses in one gate period, and at 2.5 km/h, "2" and "3" occur alternately in each gate period, resulting in two gates. The period is ``5'', and practically one gate period is ``2.5''. In addition, at 2.55 Km/h, since the increase is one pulse in 20 gate periods, while "2" and "3" occur alternately, "2" occurs in one gate period out of 20 gate periods. becomes "3", and the pulse number sequence becomes "2, 3, 2, 3, 2, 3, 3,
3, 2, 3, 2'' occurs periodically (every 20 gates). The added values in Tables 1 to 2 described later or the contents of registers 11 and 12 indicate periodic increases and decreases in the number of pulses in the gate period due to frequency changes of 1 km/h or less, and are as follows. The explanation will be based on this pulse number change.

[Means for solving problems]

In order to solve the above problems, the present invention includes a counter that counts input pulse signals for each gate period, and a count value of this counter for at least two gate periods including the latest count value. A shift register that stores data in sequence, and a coincidence discriminator that compares the latest counted value in this shift register with the counted value in the previous gate cycle, and outputs a signal when these counted values are equal, and that is displayed on a display. The contents of the latch circuit that holds the display value and the count value of the shift register are compared when the signal is output from the coincidence discriminator, and it is determined whether the count value of the shift register is large or small with respect to the display value of the latch circuit. A magnitude discriminator that outputs a discrimination signal, and a count comparator that counts the number of times the output signal of the magnitude discriminator is generated and updates the display value of the latch circuit to the latest count value when a predetermined value is reached. It is characterized by the following structure. [Operation] According to the present invention, when the difference between the current display value and the latest count value exceeds the value corresponding to the minimum display unit, the latest count value is set as the display value, and the difference is within the value corresponding to the minimum display unit. In this case, the latest count value is compared with the count value counted at the previous gate time, and when each count value is equal and this counting state has occurred a predetermined number of times, the count value is updated and displayed as the display value. Its purpose is to provide a pulse counting method that prevents flickering and prevents hysteresis errors in displayed values. [Embodiment] FIG. 3 shows a block diagram of a pulse counting circuit according to an embodiment of the present invention, in which 1 is an input terminal, 2 is
3 is a counter, 3 is a shift register, and 4 is an adder, which constitute a counting section that calculates the number of input pulses at each predetermined period. 5 is a latch circuit, 6 is a decoder driver, 7 is a display circuit, 8 is a comparator, 11, 1
2 and 13 are shift registers, 14 is a match discriminator,
15 is a magnitude discriminator, 16 is an up/down counter, and 17 is a comparator. The counter 16 and the comparator 17 constitute a counting comparator. Next, the operation of the pulse counting method of this embodiment will be explained. First, in this embodiment, the gate time is divided into two, so the pulses input from the input terminal 1 during 1/2 period of the gate time T are counted by the counter 2, and sequentially shifted to the register 3.
The adder 4 calculates the number of pulses of the gate time T (the latest counted value), and transfers it to the latch circuit 5, where the counted value of the display circuit 7 is displayed. In addition, during the counting process, the current display value in the latch circuit 5 and the latest count value in the adder 4 are compared by the comparator 8, and when the difference exceeds the minimum display unit (1 km/h in this case), the comparison A load pulse is output from the device 8 to the latch circuit 5, and the displayed value is immediately updated to the latest count value. Here, when the difference between the latest count value in the adder 4 and the current display value in the latch circuit 5 is within the minimum display unit, the added value of the adder 4 is transferred to the register 11, and each shift register 11, The stored contents of 12 and 13 are sequentially shifted. and register 11
Coincidence discriminator 1 compares the latest counted value with the counted value of register 13 counted a gate time T before
4 (because it is divided into two, three registers are required to obtain independent gate periods), and if the count values of register 11 and register 13 are equal, the register 1
Determine the magnitude relationship between the latest count value of 3 (same as the contents of register 11) and the current display value of latch circuit 5,
When the latest count value is larger than the displayed value, the up-down counter 16 adds 1, and when it is smaller, it subtracts 1, and the value of the up-down counter 16 is set to a positive or negative value preset in the comparator 17. When reaches a certain value, a load pulse is output from the comparator 17, and the displayed value is updated to the count value in the adder 4. Next, a specific example will be explained. A in Table 2 is 2Km/h
When increasing from

[Table] Registers 11 and 1 when the calculated values are shifted sequentially
3 shows the contents of register 11. At 2 km/h, as the count value of counter 2, 1/2 gate period "1" occurs three times and "2" occurs once. , 13 are input alternately as "2" and "3" when the addition value as the gate period is shifted, and the contents of registers 11 and 13 do not match, so the up-down counter 16 is no change. Next, as shown in B of Table 2, if it is slightly less than 2.5Km/h,
The count value of counter 2 is "1" 3 times or 4
Since "2" occurs once per cycle, when the pulse number "1" continues four times, registers 11 and 1
The content of 3 may be "2" and match, but the display is "2" and remains unchanged. Also, C in Table 2 is
This shows the case where the count value of counter 2 is slightly larger than 2.5 km/h, and since the count value of counter 2 mainly occurs at a rate of 3 times and 2 times, registers 11 and 13 are The content is that "2" and "3" are input alternately, but the phase shift difference between the input pulse period and gate period slightly exceeds 2.5 Km/h, and the number of pulses in each period, that is, the count value of counter 2, is " In some cases, "112" is input after "2", and in this case, the contents of registers 11 and 13 match as "3", and as a result, a signal is output from the match discriminator 14 to the magnitude comparator 15, and this By comparing the numerical value "3" with the display value "2" of the latch circuit 5, the up-down counter 1
1 is added to 6. Since the coincidence of "3" in the registers 11 and 13 occurs in the flow of pulses shown in Table 2 C, 1 is added each time in the up-down counter 16, and this up-down counter 1
When the content of 6 reaches a positive value preset by the comparator 17, the value displayed on the display 7 is updated from "2" to "3".

〔Effect of the invention〕

As is clear from the above operation, when the change in the latest count value with respect to the displayed value exceeds the minimum display unit, it is updated immediately, and when it is within that value, the displayed value is held, so that unstable minute fluctuations in the input frequency It is possible to prevent positive and negative flickering of the display unit due to deviation from the gate signal, and to provide stable display. Furthermore, by performing the comparison update process described above, it is possible to always display the value obtained by rounding up the decimal point of the input frequency to the nearest whole number, thereby preventing display errors when rising or falling due to hysteresis and stabilizing the frequency. Accurate measurement and display of time becomes possible.

[Brief explanation of drawings]

Figure 1 is a block diagram of the conventional pulse counting method.
FIG. 2 is an explanatory diagram illustrating errors due to hysteresis when the display value increases and decreases, and FIG. 3 is a block diagram of one embodiment of the present invention. 1...Input terminal, 2...Counter, 3...Register,
4... Adder, 5... Latch circuit, 6... Decoder driver, 7... Display, 11, 12, 13... Shift register, 14... Coincidence discriminator, 15... Size discriminator,
16...Up-down counter, 17...Comparator.

Claims (1)

[Claims] 1. A counter that counts input pulse signals for each gate period, a shift register that sequentially stores the counted values of this counter for at least two gate periods including the latest counted value, and Compare the count value with the count value in the previous gate period, and when these count values are equal,
The content of the match discriminator that outputs the signal, the latch circuit that holds the display value displayed on the display, and the counted value of the shift register are compared when the signal is output from the match discriminator, and the latch circuit displays the result. a size discriminator that outputs discrimination signals when the count value of the shift register is large and small, respectively;
A pulse counting method comprising a count comparator that counts the number of times the output signal of the magnitude discriminator is generated and updates the display value of the latch circuit to the latest count value when a predetermined value is reached.