JPS6485426A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To prevent out of synchronism by holding a control voltage of a voltage controlled oscillator by the phase comparison at the signal just before even if signal missing takes place so as to apply phase locking in a PLL circuit using a signal from a medium where signal missing is unavoidable as an input reference signal. CONSTITUTION:A clock missing detection circuit comprising a monostable multivibrator 1 and an AND circuit 6 and a counter 5, a gate circuit comprising a latch 7 and an AND circuit 8, a phase comparator 2, a loop filter 3, a voltage controlled oscillator 4, a frequency divider circuit 10 and an inverting circuit 9 to convert the output of the frequency divider circuit to a clear signal of the counter 5 are provided. The phase comparator 2 compares the phase of the input reference signal B with that of a comparison signal G to generate phase error signals H, J in response to the phase difference. The control voltage of the voltage controlled oscillator 4 is changed by the loop filter 3 and the voltage controlled oscillator 4 generates a signal having a frequency in response to the voltage. Thus, out of synchronism of the phase synchronizing circuit is prevented due to missing input signal and the phase error signal with a signal given instead at signal missing is not outputted.