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JPS6454542A - Virtual computer system - Google Patents

Virtual computer system

Info

Publication number
JPS6454542A
JPS6454542A JP21041587A JP21041587A JPS6454542A JP S6454542 A JPS6454542 A JP S6454542A JP 21041587 A JP21041587 A JP 21041587A JP 21041587 A JP21041587 A JP 21041587A JP S6454542 A JPS6454542 A JP S6454542A
Authority
JP
Japan
Prior art keywords
address
virtual computer
processor
bagr
computer system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21041587A
Other languages
Japanese (ja)
Other versions
JPH06105431B2 (en
Inventor
Masanori Takahashi
Satoru Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62210415A priority Critical patent/JPH06105431B2/en
Publication of JPS6454542A publication Critical patent/JPS6454542A/en
Publication of JPH06105431B2 publication Critical patent/JPH06105431B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4843Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To operate the whole processing system under a virtual computer system, by providing first and second processors, and providing a base address guard register (BAGR) on the second processor. CONSTITUTION:An accessible area by a vector unit 2 being the second processor is set extending from the highest rank address of a storage device 4 to a VU domain 10, so that the accessible area can be designated by only the contents of a BAGR 8. Accordingly, when the unit 2 executes an access, a memory access exception can be detected by only comparing a system absolute address of a result obtained by converting a logical address by an address converting mechanism, and the contents of the BAGR 8. That is, at the time of executing an operation as a virtual computer, the memory access exception can be detected, therefore, the whole processing system operated together with a scalar unit 1 being the first processor and a channel processor 3 can be operated under the virtual computer system.
JP62210415A 1987-08-25 1987-08-25 Virtual computer system in vector processor Expired - Fee Related JPH06105431B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62210415A JPH06105431B2 (en) 1987-08-25 1987-08-25 Virtual computer system in vector processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62210415A JPH06105431B2 (en) 1987-08-25 1987-08-25 Virtual computer system in vector processor

Publications (2)

Publication Number Publication Date
JPS6454542A true JPS6454542A (en) 1989-03-02
JPH06105431B2 JPH06105431B2 (en) 1994-12-21

Family

ID=16588939

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62210415A Expired - Fee Related JPH06105431B2 (en) 1987-08-25 1987-08-25 Virtual computer system in vector processor

Country Status (1)

Country Link
JP (1) JPH06105431B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8843727B2 (en) * 2004-09-30 2014-09-23 Intel Corporation Performance enhancement of address translation using translation tables covering large address spaces

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59167756A (en) * 1983-01-31 1984-09-21 Nec Corp Dispatch control system of virtual computer
JPS6126152A (en) * 1984-07-16 1986-02-05 Fujitsu Ltd Address check system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59167756A (en) * 1983-01-31 1984-09-21 Nec Corp Dispatch control system of virtual computer
JPS6126152A (en) * 1984-07-16 1986-02-05 Fujitsu Ltd Address check system

Also Published As

Publication number Publication date
JPH06105431B2 (en) 1994-12-21

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees