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JPS645229A - 4/5 nrzi code conversion system - Google Patents

4/5 nrzi code conversion system

Info

Publication number
JPS645229A
JPS645229A JP16184787A JP16184787A JPS645229A JP S645229 A JPS645229 A JP S645229A JP 16184787 A JP16184787 A JP 16184787A JP 16184787 A JP16184787 A JP 16184787A JP S645229 A JPS645229 A JP S645229A
Authority
JP
Japan
Prior art keywords
conversion
bit
dsv
code
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16184787A
Other languages
Japanese (ja)
Inventor
Tetsushi Itoi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP16184787A priority Critical patent/JPS645229A/en
Publication of JPS645229A publication Critical patent/JPS645229A/en
Pending legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To cancel the DC component of a conversion signal while keeping a DSV integration value within a prescribed limit by selecting a conversion table and applying code conversion so that the DSV integration value after conversion is converged into zero from the data representing even/odd number of the number of inverting code included in the channel bit after the conversion and the DSV integration value before the conversion. CONSTITUTION:In fixing an end bit of a channel bit subject to code conversion before to either noninverting code or an inverting code, the conversion table A comprising the channel bit whose DSV being an index of the signal DC balance is negative and the conversion table B whose DSV is positive are prepared. After data bits (4-bit) are converted into a 9-bit data by a conversion ROM 13, the low-order 5-bit and the high-order 4-bit are fed respectively to a serial/ parallel conversion circuit 14 and a DSV integration circuit 15 respectively. A table selection circuit 18 takes an exclusive OR between the output most significant bit of the integration circuit 15 and the end bit of the channel bit subject to code conversion by a gate circuit 19, and the table A or B is selected by the ROM 13 depending on the output.
JP16184787A 1987-06-29 1987-06-29 4/5 nrzi code conversion system Pending JPS645229A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16184787A JPS645229A (en) 1987-06-29 1987-06-29 4/5 nrzi code conversion system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16184787A JPS645229A (en) 1987-06-29 1987-06-29 4/5 nrzi code conversion system

Publications (1)

Publication Number Publication Date
JPS645229A true JPS645229A (en) 1989-01-10

Family

ID=15743072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16184787A Pending JPS645229A (en) 1987-06-29 1987-06-29 4/5 nrzi code conversion system

Country Status (1)

Country Link
JP (1) JPS645229A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008146745A (en) * 2006-12-11 2008-06-26 Hitachi Ltd Optical disk drive and modulation method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008146745A (en) * 2006-12-11 2008-06-26 Hitachi Ltd Optical disk drive and modulation method

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