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JPS6446341A - Buffer memory control circuit - Google Patents

Buffer memory control circuit

Info

Publication number
JPS6446341A
JPS6446341A JP62201743A JP20174387A JPS6446341A JP S6446341 A JPS6446341 A JP S6446341A JP 62201743 A JP62201743 A JP 62201743A JP 20174387 A JP20174387 A JP 20174387A JP S6446341 A JPS6446341 A JP S6446341A
Authority
JP
Japan
Prior art keywords
buffer memory
clear code
memory clear
control circuit
memory control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62201743A
Other languages
Japanese (ja)
Inventor
Yasuhiko Shima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62201743A priority Critical patent/JPS6446341A/en
Publication of JPS6446341A publication Critical patent/JPS6446341A/en
Pending legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To accurately perform data transfer, by resetting a buffer memory address signal to a prescribed buffer memory address when a buffer memory clear code is identified. CONSTITUTION:A buffer memory clear code identification circuit 8 detects a memory clear code in reception data transmitted from transmission side. And a counter 1 for a reception clock signal sets the buffer memory address signal in the midpoint of a buffer memory based on the output of the buffer memory clear code identification circuit 8. Also, a gate circuit 9 inhibits the delivery of the buffer memory clear code as read data. In such a way, since it is possble to guarantee the prevention of generation of slippage for a certain time after receiving the buffer memory clear code, it is possible to perform the data transfer accurately.
JP62201743A 1987-08-14 1987-08-14 Buffer memory control circuit Pending JPS6446341A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62201743A JPS6446341A (en) 1987-08-14 1987-08-14 Buffer memory control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62201743A JPS6446341A (en) 1987-08-14 1987-08-14 Buffer memory control circuit

Publications (1)

Publication Number Publication Date
JPS6446341A true JPS6446341A (en) 1989-02-20

Family

ID=16446203

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62201743A Pending JPS6446341A (en) 1987-08-14 1987-08-14 Buffer memory control circuit

Country Status (1)

Country Link
JP (1) JPS6446341A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02226930A (en) * 1989-02-28 1990-09-10 Meidensha Corp Transmission delay phase compensation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02226930A (en) * 1989-02-28 1990-09-10 Meidensha Corp Transmission delay phase compensation circuit

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