[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JPS6441044A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS6441044A
JPS6441044A JP62195244A JP19524487A JPS6441044A JP S6441044 A JPS6441044 A JP S6441044A JP 62195244 A JP62195244 A JP 62195244A JP 19524487 A JP19524487 A JP 19524487A JP S6441044 A JPS6441044 A JP S6441044A
Authority
JP
Japan
Prior art keywords
data
parallel
received
reading
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62195244A
Other languages
Japanese (ja)
Inventor
Masahiro Ichihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62195244A priority Critical patent/JPS6441044A/en
Publication of JPS6441044A publication Critical patent/JPS6441044A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To increase the data transfer speed to a data processing system by controlling the data reading/writing jobs in parallel to plural disk memories. CONSTITUTION:When a data writing command is received, a master controller 2 divides 8 bytes received in parallel from a data processing system 1 into 2-byte widths. Then each 2-byte width is written into four data buffers with the same address respectively. When a data reading command is received, the controller 2 monitors whether or not all slave controllers 4 complete the reading of data out of a disk memory 5 via a single data block and then the data are stored in each buffer 3. When the end of storage of those data are detected, the controller 2 reads the data in parallel out of the same address of each buffer 3 and edits these data into the data of the 8-byte width (4 times the 2-byte width) to transfer the data to the system 1. In such a way, the data transfer speed is increased to the system 1.
JP62195244A 1987-08-06 1987-08-06 Data transfer system Pending JPS6441044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62195244A JPS6441044A (en) 1987-08-06 1987-08-06 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62195244A JPS6441044A (en) 1987-08-06 1987-08-06 Data transfer system

Publications (1)

Publication Number Publication Date
JPS6441044A true JPS6441044A (en) 1989-02-13

Family

ID=16337892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62195244A Pending JPS6441044A (en) 1987-08-06 1987-08-06 Data transfer system

Country Status (1)

Country Link
JP (1) JPS6441044A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6938417B2 (en) 2001-12-03 2005-09-06 The Tokyo Electric Power Company, Incorporated Exhaust heat recovery system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6938417B2 (en) 2001-12-03 2005-09-06 The Tokyo Electric Power Company, Incorporated Exhaust heat recovery system

Similar Documents

Publication Publication Date Title
ES8609770A1 (en) Memory access control system.
WO1995006284B1 (en) Ata interface architecture employing state machines
JPS6419438A (en) Hot stand-by memory copy system
EP0312238A3 (en) Fifo buffer controller
KR890003688B1 (en) Buffer-storage control system
EP0398189A3 (en) Noncacheable address random access memory
JPS55115121A (en) Input and output control unit possible for duplicated recording
JPS6441044A (en) Data transfer system
IE872505L (en) Executing the instruction sequences in an order determined¹in advance
JPS6476346A (en) Disk cache control system
GB9019891D0 (en) Computer memory array control
JPS54148328A (en) Buffer memory control system
JPS57120144A (en) Data transfer system
JPS5745658A (en) Data storage system
JPS5730014A (en) Input and output system
JPS57199062A (en) Disc controller
JPS6473415A (en) Optical disk sub-system
JPS6454529A (en) Data processing control system
JPS5564693A (en) Buffer memory unit
KR940009830B1 (en) Control logic device
JPS5730179A (en) Buffer memory control system
JPS57197661A (en) Multiplex controlling system for file memory
EP0049112A2 (en) Method and apparatus for controlling writing and reading of data in cassette memories
JPS55119728A (en) Multichannel control system
JPS569826A (en) Channel controller