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JPS644091A - Plating - Google Patents

Plating

Info

Publication number
JPS644091A
JPS644091A JP15910087A JP15910087A JPS644091A JP S644091 A JPS644091 A JP S644091A JP 15910087 A JP15910087 A JP 15910087A JP 15910087 A JP15910087 A JP 15910087A JP S644091 A JPS644091 A JP S644091A
Authority
JP
Japan
Prior art keywords
plating
current density
beginning
wiring
concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15910087A
Other languages
Japanese (ja)
Inventor
Yoshio Watanabe
Kenji Osawa
Kunihiko Tokura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP15910087A priority Critical patent/JPS644091A/en
Publication of JPS644091A publication Critical patent/JPS644091A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To cause a plating layer to be biasedly formed only in the thickness direction of a pattern wiring by giving a specific value to the composition of the plating sulution at the time of performing the wiring reinforcement of the wiring circuit, thereby increasing the plating current density from the beginning of the plating to the ending of the plating. CONSTITUTION:When an electrolytic plating is performed, a wiring substrate 1 on which etching layers 4 are formed is dipped in a plating both 6 as the cathode, and a copper plate 7 is dipped as the anode. The copper sulfate concentration of a plating solution 9 in the plating bath is made to fall in the range of saturation concentration 100g/l-, that it, saturation concentration 25g/l- as the copper concentration. And the current density for the electrolyte plating is changed stepwise or continuously within the range of 5-60A/dm<2>. Particularly, it is increased multistepwise or continuously from the beginning of the plating to the ending of the plating so that the plating current density at the beginning of the plating is 5-15A/dm<2> and the plating current density at the end of the plating is 35-60A/dm<2>.
JP15910087A 1987-06-26 1987-06-26 Plating Pending JPS644091A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15910087A JPS644091A (en) 1987-06-26 1987-06-26 Plating

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15910087A JPS644091A (en) 1987-06-26 1987-06-26 Plating

Publications (1)

Publication Number Publication Date
JPS644091A true JPS644091A (en) 1989-01-09

Family

ID=15686236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15910087A Pending JPS644091A (en) 1987-06-26 1987-06-26 Plating

Country Status (1)

Country Link
JP (1) JPS644091A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000080496A (en) * 1998-09-03 2000-03-21 Ebara Corp Filling plating method for base material having fine pore and/or fine groove
JP2005272874A (en) * 2004-03-23 2005-10-06 Sumitomo Bakelite Co Ltd Method for producing circuit board
JP2007335470A (en) * 2006-06-12 2007-12-27 Hitachi Cable Ltd Method of forming conductor pattern
US20150035640A1 (en) * 2013-08-02 2015-02-05 Cyntec Co., Ltd. Method of manufacturing multi-layer coil and multi-layer coil device
JP2016009854A (en) * 2014-06-26 2016-01-18 住友電工プリントサーキット株式会社 Printed wiring board, electronic component, and method for manufacturing printed wiring board
CN108417340A (en) * 2014-09-22 2018-08-17 三星电机株式会社 Multilayer seed pattern inductor, its manufacturing method and the plate with it
CN108701538A (en) * 2016-03-31 2018-10-23 摩达伊诺琴股份有限公司 Coil pattern and forming method thereof and chip device comprising it
JP2020513475A (en) * 2016-11-18 2020-05-14 ハッチンソン テクノロジー インコーポレイテッドＨｕｔｃｈｉｎｓｏｎ Ｔｅｃｈｎｏｌｏｇｙ Ｉｎｃｏｒｐｏｒａｔｅｄ High aspect ratio electroplating structure and anisotropic electroplating process
US11387033B2 (en) 2016-11-18 2022-07-12 Hutchinson Technology Incorporated High-aspect ratio electroplated structures and anisotropic electroplating processes
US11521785B2 (en) 2016-11-18 2022-12-06 Hutchinson Technology Incorporated High density coil design and process

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000080496A (en) * 1998-09-03 2000-03-21 Ebara Corp Filling plating method for base material having fine pore and/or fine groove
JP2005272874A (en) * 2004-03-23 2005-10-06 Sumitomo Bakelite Co Ltd Method for producing circuit board
JP2007335470A (en) * 2006-06-12 2007-12-27 Hitachi Cable Ltd Method of forming conductor pattern
US10217563B2 (en) * 2013-08-02 2019-02-26 Cyntec Co., Ltd. Method of manufacturing multi-layer coil and multi-layer coil device
US20150035640A1 (en) * 2013-08-02 2015-02-05 Cyntec Co., Ltd. Method of manufacturing multi-layer coil and multi-layer coil device
CN104347262A (en) * 2013-08-02 2015-02-11 乾坤科技股份有限公司 Method for manufacturing multilayer coil and magnetic device
CN104347262B (en) * 2013-08-02 2017-04-12 乾坤科技股份有限公司 Method for manufacturing multilayer coil
CN107331491A (en) * 2013-08-02 2017-11-07 乾坤科技股份有限公司 Magnetic device
JP2016009854A (en) * 2014-06-26 2016-01-18 住友電工プリントサーキット株式会社 Printed wiring board, electronic component, and method for manufacturing printed wiring board
CN108417340A (en) * 2014-09-22 2018-08-17 三星电机株式会社 Multilayer seed pattern inductor, its manufacturing method and the plate with it
CN108417340B (en) * 2014-09-22 2020-05-26 三星电机株式会社 Multilayer seed pattern inductor, method of manufacturing the same, and board having the same
US11276520B2 (en) 2014-09-22 2022-03-15 Samsung Electro-Mechanics Co., Ltd. Multilayer seed pattern inductor, manufacturing method thereof, and board having the same
CN108701538A (en) * 2016-03-31 2018-10-23 摩达伊诺琴股份有限公司 Coil pattern and forming method thereof and chip device comprising it
JP2019508906A (en) * 2016-03-31 2019-03-28 モダ−イノチップス シーオー エルティディー Coil pattern, method of forming the same, and chip element provided with the same
US11069472B2 (en) 2016-03-31 2021-07-20 Moda-Innochips Co., Ltd. Coil pattern, method for forming same, and chip device including same
JP2020513475A (en) * 2016-11-18 2020-05-14 ハッチンソン テクノロジー インコーポレイテッドＨｕｔｃｈｉｎｓｏｎ Ｔｅｃｈｎｏｌｏｇｙ Ｉｎｃｏｒｐｏｒａｔｅｄ High aspect ratio electroplating structure and anisotropic electroplating process
US11387033B2 (en) 2016-11-18 2022-07-12 Hutchinson Technology Incorporated High-aspect ratio electroplated structures and anisotropic electroplating processes
US11521785B2 (en) 2016-11-18 2022-12-06 Hutchinson Technology Incorporated High density coil design and process
JP2022184833A (en) * 2016-11-18 2022-12-13 ハッチンソン テクノロジー インコーポレイテッド High-aspect-ratio electroplated structure and anisotropic electroplated process

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