JPS6438084U - - Google Patents
Info
- Publication number
- JPS6438084U JPS6438084U JP12856287U JP12856287U JPS6438084U JP S6438084 U JPS6438084 U JP S6438084U JP 12856287 U JP12856287 U JP 12856287U JP 12856287 U JP12856287 U JP 12856287U JP S6438084 U JPS6438084 U JP S6438084U
- Authority
- JP
- Japan
- Prior art keywords
- output
- pulse width
- circuit
- receiving
- demodulating circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Selective Calling Equipment (AREA)
Description
第１図はこの考案の一実施例のブロツク図、第
２図はパルス幅弁別回路の回路構成図、第３図は
送信装置の動作説明のためのタイミングチヤート
、第４図はパルス幅弁別回路の動作説明のための
タイミングチヤート、第５図は送信装置と受信装
置の動作説明のためのタイミングチヤート、第６
図は従来例のブロツク図である。
７……アンテナ、８……受信回路、１３……パ
ルス幅弁別回路、１４……カウンタ。
Figure 1 is a block diagram of an embodiment of this invention, Figure 2 is a circuit diagram of a pulse width discrimination circuit, Figure 3 is a timing chart for explaining the operation of the transmitter, and Figure 4 is a pulse width discrimination circuit. FIG. 5 is a timing chart for explaining the operation of the transmitting device and the receiving device.
The figure is a block diagram of a conventional example. 7... Antenna, 8... Receiving circuit, 13... Pulse width discrimination circuit, 14... Counter.
Claims (1)
、該受信素子の出力を復調する復調回路とを備え
、該復調回路の出力を受信出力となす受信装置に
おいて、前記復調回路の出力側に、パルス列信号
の各パルス幅を判別するパルス幅弁別回路と、該
パルス幅弁別回路の出力を単位時間毎に計数する
カウンタとを直列に接続したことを特徴とする受
信装置。 In a receiving device comprising a receiving element that receives a modulated pulse train signal and a demodulating circuit that demodulates the output of the receiving element, the output of the demodulating circuit is used as a receiving output, the pulse train signal is connected to the output side of the demodulating circuit. 1. A receiving device comprising a pulse width discriminator circuit for discriminating each pulse width, and a counter for counting the output of the pulse width discriminator circuit for each unit time, which are connected in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12856287U JPH0413904Y2 (en) | 1987-08-26 | 1987-08-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12856287U JPH0413904Y2 (en) | 1987-08-26 | 1987-08-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6438084U true JPS6438084U (en) | 1989-03-07 |
| JPH0413904Y2 JPH0413904Y2 (en) | 1992-03-30 |
Family
ID=31382017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12856287U Expired JPH0413904Y2 (en) | 1987-08-26 | 1987-08-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0413904Y2 (en) |
-
1987
- 1987-08-26 JP JP12856287U patent/JPH0413904Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0413904Y2 (en) | 1992-03-30 |
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