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JPS643748A - Test device for software logical device - Google Patents

Test device for software logical device

Info

Publication number
JPS643748A
JPS643748A JP62157694A JP15769487A JPS643748A JP S643748 A JPS643748 A JP S643748A JP 62157694 A JP62157694 A JP 62157694A JP 15769487 A JP15769487 A JP 15769487A JP S643748 A JPS643748 A JP S643748A
Authority
JP
Japan
Prior art keywords
memory
test
arithmetic element
address
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62157694A
Other languages
Japanese (ja)
Inventor
Yukio Nagaoka
Satoru Suzuki
Shigeru Izumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62157694A priority Critical patent/JPS643748A/en
Publication of JPS643748A publication Critical patent/JPS643748A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing And Monitoring For Control Systems (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE:To inspect a logical function in a small number of test cases by adding a memory contents reading means of a device to be tested and a test pattern generating means which produces the output value of each basic arithmetic element as well as a test input signal to a test device. CONSTITUTION:A test device 1 gives an input pattern to a software logical device 2 and fetches the final stage value of a logic circuit from an output part 23 via a signal input means 15. A memory contents reading means 14 reads the output value of each basic arithmetic element out of an arithmetic element output memory 25 and sends it to a comparison means 16. A variable address memory means 33 stores the address of the memory 25 and the means 14 reads the address of the memory 25 out of the means 33. Then the means 14 reads the output value of the basic arithmetic element out of the corresponding address of the memory 25. A comparison means 16 compares the test results given from both means 14 and 15 with a reference pattern received from a test case selection means 12. The result of this comparison is delivered to a result output means 17.
JP62157694A 1987-06-26 1987-06-26 Test device for software logical device Pending JPS643748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62157694A JPS643748A (en) 1987-06-26 1987-06-26 Test device for software logical device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62157694A JPS643748A (en) 1987-06-26 1987-06-26 Test device for software logical device

Publications (1)

Publication Number Publication Date
JPS643748A true JPS643748A (en) 1989-01-09

Family

ID=15655341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62157694A Pending JPS643748A (en) 1987-06-26 1987-06-26 Test device for software logical device

Country Status (1)

Country Link
JP (1) JPS643748A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0580816A (en) * 1991-09-19 1993-04-02 Toyota Auto Body Co Ltd Device for evaluating line control circuit
JPH07160313A (en) * 1993-12-03 1995-06-23 Meiwa Kogyo Kk Sequence program check device
JPH07225605A (en) * 1994-02-09 1995-08-22 Riyoosen Engineers:Kk Simulator for sequencer
JP2000122707A (en) * 1998-10-20 2000-04-28 Hitachi Ltd Testing method for checking function for programmable controller and plant monitor and control device
JP2002163020A (en) * 2000-11-27 2002-06-07 Matsushita Electric Works Ltd Method and device for detecting abnormality in programmable controller
JP2009294918A (en) * 2008-06-05 2009-12-17 Toshiba Mitsubishi-Electric Industrial System Corp Plant control system
US8060221B2 (en) 2006-06-13 2011-11-15 Mitsubishi Electric Corporation Peripheral device of programmable logic controller
JP2017167652A (en) * 2016-03-14 2017-09-21 オムロン株式会社 Evaluation system, evaluation program, and evaluation method
JP6395967B1 (en) * 2017-06-23 2018-09-26 三菱電機株式会社 Program verification system, control device, and program verification method

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0580816A (en) * 1991-09-19 1993-04-02 Toyota Auto Body Co Ltd Device for evaluating line control circuit
JPH07160313A (en) * 1993-12-03 1995-06-23 Meiwa Kogyo Kk Sequence program check device
JPH07225605A (en) * 1994-02-09 1995-08-22 Riyoosen Engineers:Kk Simulator for sequencer
JP2000122707A (en) * 1998-10-20 2000-04-28 Hitachi Ltd Testing method for checking function for programmable controller and plant monitor and control device
JP2002163020A (en) * 2000-11-27 2002-06-07 Matsushita Electric Works Ltd Method and device for detecting abnormality in programmable controller
US8060221B2 (en) 2006-06-13 2011-11-15 Mitsubishi Electric Corporation Peripheral device of programmable logic controller
JP4890545B2 (en) * 2006-06-13 2012-03-07 三菱電機株式会社 Peripheral device of programmable logic controller
JP2009294918A (en) * 2008-06-05 2009-12-17 Toshiba Mitsubishi-Electric Industrial System Corp Plant control system
JP2017167652A (en) * 2016-03-14 2017-09-21 オムロン株式会社 Evaluation system, evaluation program, and evaluation method
US10180892B2 (en) 2016-03-14 2019-01-15 Omron Corporation Evaluation system, non-transitory storage medium storing thereon evaluation program, and evaluation method
JP6395967B1 (en) * 2017-06-23 2018-09-26 三菱電機株式会社 Program verification system, control device, and program verification method
WO2018235250A1 (en) * 2017-06-23 2018-12-27 三菱電機株式会社 Program verifying system, control apparatus, and program verifying method
CN109643095A (en) * 2017-06-23 2019-04-16 三菱电机株式会社 Program authentication system, control device and program verification method
US20190302739A1 (en) * 2017-06-23 2019-10-03 Mitsubishi Electric Corporation Program verification system, control apparatus, and program verification method

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