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JPS6436051A - Wiring structure - Google Patents

Wiring structure

Info

Publication number
JPS6436051A
JPS6436051A JP19232387A JP19232387A JPS6436051A JP S6436051 A JPS6436051 A JP S6436051A JP 19232387 A JP19232387 A JP 19232387A JP 19232387 A JP19232387 A JP 19232387A JP S6436051 A JPS6436051 A JP S6436051A
Authority
JP
Japan
Prior art keywords
layer
insulating film
interlayer insulating
tungsten silicide
silicide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19232387A
Other languages
Japanese (ja)
Inventor
Yukiyasu Sugano
Kazuhide Koyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP19232387A priority Critical patent/JPS6436051A/en
Publication of JPS6436051A publication Critical patent/JPS6436051A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To reduce a contact resistance value by a method wherein an interlayer insulating film, a titanium layer and a tungsten silicide layer formed along the surface of the titanium layer are formed on a semiconductor so that the layer is hard to exfoliate. CONSTITUTION:After an interlayer insulating film 2 has been formed on a semiconductor layer 1, a contact hole 3 is made in the interlayer insulating film 2; a titanium layer 4 is formed on the semiconductor layer 1 inside the contact hole 3 and on the interlayer insulating film 2 by a magnetron sputtering operation. Then a tungsten silicide layer 5 is formed on the titanium layer 4 by a low-pressure CVD operation. During this process, the contact hole 3 is filled completely with the tungsten silicide layer 5. The tungsten silicide layer 5 and the titanium layer 4 are etched back selectively by an RIE operation; the interlayer insulating film 2 is exposed. By this setup, the tungsten silicide layer is hard to exfoliate; a resistance value can be reduced.
JP19232387A 1987-07-31 1987-07-31 Wiring structure Pending JPS6436051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19232387A JPS6436051A (en) 1987-07-31 1987-07-31 Wiring structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19232387A JPS6436051A (en) 1987-07-31 1987-07-31 Wiring structure

Publications (1)

Publication Number Publication Date
JPS6436051A true JPS6436051A (en) 1989-02-07

Family

ID=16289369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19232387A Pending JPS6436051A (en) 1987-07-31 1987-07-31 Wiring structure

Country Status (1)

Country Link
JP (1) JPS6436051A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5110762A (en) * 1988-07-07 1992-05-05 Kabushiki Kaisha Toshiba Manufacturing a wiring formed inside a semiconductor device
US5371041A (en) * 1988-02-11 1994-12-06 Sgs-Thomson Microelectronics, Inc. Method for forming a contact/VIA

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5371041A (en) * 1988-02-11 1994-12-06 Sgs-Thomson Microelectronics, Inc. Method for forming a contact/VIA
US5110762A (en) * 1988-07-07 1992-05-05 Kabushiki Kaisha Toshiba Manufacturing a wiring formed inside a semiconductor device

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