JPS6430458U - - Google Patents
Info
- Publication number
- JPS6430458U JPS6430458U JP12402787U JP12402787U JPS6430458U JP S6430458 U JPS6430458 U JP S6430458U JP 12402787 U JP12402787 U JP 12402787U JP 12402787 U JP12402787 U JP 12402787U JP S6430458 U JPS6430458 U JP S6430458U
- Authority
- JP
- Japan
- Prior art keywords
- pogo pin
- utility
- internal conductor
- substrate
- handler
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 4
- 238000000926 separation method Methods 0.000 claims 2
- 239000012212 insulator Substances 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 102100036464 Activated RNA polymerase II transcriptional coactivator p15 Human genes 0.000 description 1
- 101000713904 Homo sapiens Activated RNA polymerase II transcriptional coactivator p15 Proteins 0.000 description 1
- 208000017493 Pelizaeus-Merzbacher disease Diseases 0.000 description 1
- 229910004444 SUB1 Inorganic materials 0.000 description 1
- 229910004438 SUB2 Inorganic materials 0.000 description 1
- 101150080287 SUB3 gene Proteins 0.000 description 1
- 101150023658 SUB4 gene Proteins 0.000 description 1
- 101100311330 Schizosaccharomyces pombe (strain 972 / ATCC 24843) uap56 gene Proteins 0.000 description 1
- 201000001438 hypomyelinating leukodystrophy 2 Diseases 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 101150018444 sub2 gene Proteins 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
第1図は、ICハンドラに用いられるテストヘ
ツド部を構成するプローブとしてのボゴピン基板
の一実施例の平面図、第2図は、その一実施例を
示す要部断面図、第3図は、その他の一実施例を
示す要部断面図、第4図は、複数のICソケツト
に対応したポゴピン基板の一実施例を示す平面図
、第5図は、この考案に用いられるICハンドラ
における測定部の一実施例の概略側面図、第6図
は、上記第1図に対応し、その作動形態を説明す
るための概略側面図、第7図は、従来のポゴピン
基板の一例を示す平面図である。
PP……ポゴピン、SUB……基板、SUB1
,SUB3……絶縁層、SUB2……導電体、H
OL……空間、HD……半田、SP……スペーサ
ー、HLD1,HLD2……連結体、AS……エ
アーシリンダ、AM……アーム、SF……シヤフ
ト、GD……ガイド機構、CB……コンタクトブ
ロツク、TR……搬送レール、CN……ICソケ
ツト、TH……テストヘツド、BS……テストベ
ース、Z,X……調整板、SUB4……絶縁基板
、PPS……信号用ポゴピン、PPG……接地用
ポゴピン、PT1,PT2……配線パターン。
FIG. 1 is a plan view of an embodiment of a bogo pin board as a probe constituting a test head used in an IC handler, FIG. FIG. 4 is a plan view showing an embodiment of a pogo pin board compatible with a plurality of IC sockets, and FIG. A schematic side view of one embodiment, FIG. 6, corresponds to the above-mentioned FIG. 1, and is a schematic side view for explaining its operating form, and FIG. 7 is a plan view showing an example of a conventional pogo pin board. . PP...pogo pin, SUB...board, SUB1
, SUB3... Insulating layer, SUB2... Conductor, H
OL...Space, HD...Solder, SP...Spacer, HLD1, HLD2...Connection body, AS...Air cylinder, AM...Arm, SF...Shaft, GD...Guide mechanism, CB...Contact block , TR...transport rail, CN...IC socket, TH...test head, BS...test base, Z, X...adjustment plate, SUB4...insulating board, PPS...signal pogo pin, PPG...grounding Pogo pin, PT1, PT2...Wiring pattern.
Claims (1)
定すべきICが装填されるICソケツトの電極に
対応した位置に上記基板を貫通するようにその内
部導電体とは電気的に分離されて設けられる双頭
のポゴピンとを含むテストヘツドを含むことを特
徴とするICハンドラ。 2 上記基板の一方からポゴピンが挿入されるこ
とによつて他方に突出する部分の絶縁層の表面に
は、上記ポゴピンを半田付けする電極が設けられ
るものであることを特徴とする実用新案登録請求
の範囲第1項記載のICハンドラ。 3 上記基板の内部導電体とポゴピンとの間の電
気的分離は、内部導電体を貫通する孔が、上記ポ
ゴピンのそれより大きな径とされることによつて
空間分離されるものであることを特徴とする実用
新案登録請求の範囲第1又は第2項記載のICハ
ンドラ。 3 上記基板の内部導電体とポゴピンとの間の電
気的分離は、内部導電体を貫通する孔が、上記ポ
ゴピンのそれより大きな径とされ、それに筒状の
絶縁体からなるスペーサーが設けられることによ
つて行われるものであることを特徴とする実用新
案登録請求の範囲第1又は第2項記載のICハン
ドラ。[Claims for Utility Model Registration] 1. A conductive substrate with an insulating layer formed on its surface, and an internal conductor extending through the substrate at a position corresponding to the electrode of an IC socket into which an IC to be measured is loaded. What is claimed is: 1. An IC handler comprising: a test head including a double-headed pogo pin that is electrically isolated from the test head; 2. A request for registration of a utility model, characterized in that the surface of the insulating layer of the portion of the board that protrudes from one side of the substrate when the pogo pin is inserted therein is provided with an electrode to which the pogo pin is soldered. The IC handler according to the scope of item 1. 3. The electrical separation between the internal conductor of the substrate and the pogo pin is spatially separated by a hole passing through the internal conductor having a diameter larger than that of the pogo pin. An IC handler according to claim 1 or 2 of the claimed utility model registration. 3. Electrical separation between the internal conductor of the board and the pogo pin is achieved by making the hole penetrating the internal conductor have a larger diameter than that of the pogo pin, and providing a spacer made of a cylindrical insulator therewith. The IC handler according to claim 1 or 2 of the utility model registration claim, characterized in that the IC handler is operated by a utility model.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12402787U JPS6430458U (en) | 1987-08-13 | 1987-08-13 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12402787U JPS6430458U (en) | 1987-08-13 | 1987-08-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6430458U true JPS6430458U (en) | 1989-02-23 |
Family
ID=31373407
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12402787U Pending JPS6430458U (en) | 1987-08-13 | 1987-08-13 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6430458U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5728379B2 (en) * | 1977-03-01 | 1982-06-16 | ||
JPS6427170A (en) * | 1987-07-22 | 1989-01-30 | Nippon Denshi Zairyo Kk | Electromagnetically shielded socket for probe card |
-
1987
- 1987-08-13 JP JP12402787U patent/JPS6430458U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5728379B2 (en) * | 1977-03-01 | 1982-06-16 | ||
JPS6427170A (en) * | 1987-07-22 | 1989-01-30 | Nippon Denshi Zairyo Kk | Electromagnetically shielded socket for probe card |
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