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JPS6429927A - Pipeline system arithmetic circuit - Google Patents

Pipeline system arithmetic circuit

Info

Publication number
JPS6429927A
JPS6429927A JP62185974A JP18597487A JPS6429927A JP S6429927 A JPS6429927 A JP S6429927A JP 62185974 A JP62185974 A JP 62185974A JP 18597487 A JP18597487 A JP 18597487A JP S6429927 A JPS6429927 A JP S6429927A
Authority
JP
Japan
Prior art keywords
signal
register
shift error
logic
outputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62185974A
Other languages
Japanese (ja)
Inventor
Naoki Nishio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP62185974A priority Critical patent/JPS6429927A/en
Publication of JPS6429927A publication Critical patent/JPS6429927A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To easily check the generation of a shift error, by detecting the coincidence/discrepancy of a signal to be inputted to a pair of input/output bits in a register at the final stage. CONSTITUTION:The input/output bits D0 and Q0 in the register 11 are utilized for the detection of the shift error. A flip-flop circuit 15 outputs the signal of logic 1 and that of logic 0 alternately at every clock signal supplied from a terminal 21. When the shift error is generated in a certain register and the signal to be inputted to the input bit D0 of the register coincides with the signal to be outputted from the output bit Q0, it is shifted to the register 11m+1 at the final stage, and the signal of logic 1 is outputted from an exclusive OR circuit 18. In such a way, the signal outputted from a terminal Q in a flip-flop circuit 20 rises, which displays the generation of the shift error.
JP62185974A 1987-07-24 1987-07-24 Pipeline system arithmetic circuit Pending JPS6429927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62185974A JPS6429927A (en) 1987-07-24 1987-07-24 Pipeline system arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62185974A JPS6429927A (en) 1987-07-24 1987-07-24 Pipeline system arithmetic circuit

Publications (1)

Publication Number Publication Date
JPS6429927A true JPS6429927A (en) 1989-01-31

Family

ID=16180134

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62185974A Pending JPS6429927A (en) 1987-07-24 1987-07-24 Pipeline system arithmetic circuit

Country Status (1)

Country Link
JP (1) JPS6429927A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010071063A1 (en) * 2008-12-16 2010-06-24 国立大学法人 東京大学 Semiconductor integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010071063A1 (en) * 2008-12-16 2010-06-24 国立大学法人 東京大学 Semiconductor integrated circuit
JP2010147580A (en) * 2008-12-16 2010-07-01 Univ Of Tokyo Semiconductor integrated circuit

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