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JPS6425427A - Connection of semiconductor element - Google Patents

Connection of semiconductor element

Info

Publication number
JPS6425427A
JPS6425427A JP62182745A JP18274587A JPS6425427A JP S6425427 A JPS6425427 A JP S6425427A JP 62182745 A JP62182745 A JP 62182745A JP 18274587 A JP18274587 A JP 18274587A JP S6425427 A JPS6425427 A JP S6425427A
Authority
JP
Japan
Prior art keywords
semiconductor element
patterned
layer
easily align
planar connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62182745A
Other languages
Japanese (ja)
Inventor
Yoshifumi Moriyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62182745A priority Critical patent/JPS6425427A/en
Publication of JPS6425427A publication Critical patent/JPS6425427A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To easily align a semiconductor element to be placed or patterned in wiring on a substrate by forming a wide electrode region in which its side of one direction is increased in length on the element to be supplied for a simultaneous planar connection. CONSTITUTION:A resin insulating layer 4 is formed to be patterned on a semiconductor element 1 having a passivation film 3 having a predetermined opening on an aluminum electrode 2. Then, a metal film is formed by a sputtering method, a vacuum depositing method or a plating method or the like on the layer 4, and patterned to obtain an upper conductor layer 5. In this case, the electrodes made of the layer 4 are so designed that the side of at least one direction is longer than the side of the original electrode 2 to be easily align at the time of connecting to other semiconductor element in later step. As a result, a simultaneous planar connection can be performed in the aligning accuracy at a placing substrate level, thereby achieving a mass productivity applied by a normal assembling line.
JP62182745A 1987-07-21 1987-07-21 Connection of semiconductor element Pending JPS6425427A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62182745A JPS6425427A (en) 1987-07-21 1987-07-21 Connection of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62182745A JPS6425427A (en) 1987-07-21 1987-07-21 Connection of semiconductor element

Publications (1)

Publication Number Publication Date
JPS6425427A true JPS6425427A (en) 1989-01-27

Family

ID=16123694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62182745A Pending JPS6425427A (en) 1987-07-21 1987-07-21 Connection of semiconductor element

Country Status (1)

Country Link
JP (1) JPS6425427A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5226751A (en) * 1992-02-04 1993-07-13 Doleshal Donald L Controlling the environment around a submerged pile or other structures by encapsulation, and treating and repairing the encapsulation area
JP2001352174A (en) * 2000-02-25 2001-12-21 Ibiden Co Ltd Multi-layer printed wiring board and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5226751A (en) * 1992-02-04 1993-07-13 Doleshal Donald L Controlling the environment around a submerged pile or other structures by encapsulation, and treating and repairing the encapsulation area
JP2001352174A (en) * 2000-02-25 2001-12-21 Ibiden Co Ltd Multi-layer printed wiring board and method for manufacturing the same

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