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JPS5395540A - Multi-input adder - Google Patents

Multi-input adder

Info

Publication number
JPS5395540A
JPS5395540A JP1040277A JP1040277A JPS5395540A JP S5395540 A JPS5395540 A JP S5395540A JP 1040277 A JP1040277 A JP 1040277A JP 1040277 A JP1040277 A JP 1040277A JP S5395540 A JPS5395540 A JP S5395540A
Authority
JP
Japan
Prior art keywords
input adder
conversion circuit
voltage
circuit converting
constituents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1040277A
Other languages
Japanese (ja)
Inventor
Mamoru Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1040277A priority Critical patent/JPS5395540A/en
Publication of JPS5395540A publication Critical patent/JPS5395540A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To decrease the number of constituents and to reduce the number of transistor stages, by multi-connecting in row and line direction the multi-input adders consisting of the DA conversion circuit converting the number of logical 1 into a voltage and the AD conversion circuit converting the voltage quantity into binary code.
JP1040277A 1977-02-01 1977-02-01 Multi-input adder Pending JPS5395540A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1040277A JPS5395540A (en) 1977-02-01 1977-02-01 Multi-input adder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1040277A JPS5395540A (en) 1977-02-01 1977-02-01 Multi-input adder

Publications (1)

Publication Number Publication Date
JPS5395540A true JPS5395540A (en) 1978-08-21

Family

ID=11749136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1040277A Pending JPS5395540A (en) 1977-02-01 1977-02-01 Multi-input adder

Country Status (1)

Country Link
JP (1) JPS5395540A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53112626A (en) * 1977-03-14 1978-10-02 Toshiba Corp Addition/subtraction system for plural input data
JPS59116853A (en) * 1982-12-20 1984-07-05 スペリ・コ−ポレ−シヨン Apparatus for creating multiplication pipeline of arbitrary size
JPH08139613A (en) * 1994-11-15 1996-05-31 Nec Corp Code coincidence detecting system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53112626A (en) * 1977-03-14 1978-10-02 Toshiba Corp Addition/subtraction system for plural input data
JPS5624298B2 (en) * 1977-03-14 1981-06-05
JPS59116853A (en) * 1982-12-20 1984-07-05 スペリ・コ−ポレ−シヨン Apparatus for creating multiplication pipeline of arbitrary size
JPH08139613A (en) * 1994-11-15 1996-05-31 Nec Corp Code coincidence detecting system

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