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JPS5339024A - Semiconductor memory unit - Google Patents

Semiconductor memory unit

Info

Publication number
JPS5339024A
JPS5339024A JP11404976A JP11404976A JPS5339024A JP S5339024 A JPS5339024 A JP S5339024A JP 11404976 A JP11404976 A JP 11404976A JP 11404976 A JP11404976 A JP 11404976A JP S5339024 A JPS5339024 A JP S5339024A
Authority
JP
Japan
Prior art keywords
semiconductor memory
memory unit
potential
memory
sourve
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11404976A
Other languages
Japanese (ja)
Other versions
JPS5918795B2 (en
Inventor
Toshio Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP51114049A priority Critical patent/JPS5918795B2/en
Publication of JPS5339024A publication Critical patent/JPS5339024A/en
Publication of JPS5918795B2 publication Critical patent/JPS5918795B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To obtain a semiconductor memory unit featuring a good memory holding property by setting the sourve potential of a memory transistor Tr to the basic potential at the reading action time.
JP51114049A 1976-09-22 1976-09-22 semiconductor storage device Expired JPS5918795B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51114049A JPS5918795B2 (en) 1976-09-22 1976-09-22 semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51114049A JPS5918795B2 (en) 1976-09-22 1976-09-22 semiconductor storage device

Publications (2)

Publication Number Publication Date
JPS5339024A true JPS5339024A (en) 1978-04-10
JPS5918795B2 JPS5918795B2 (en) 1984-04-28

Family

ID=14627744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51114049A Expired JPS5918795B2 (en) 1976-09-22 1976-09-22 semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS5918795B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130288A (en) * 1981-02-03 1982-08-12 Nec Corp Nonvolatile storage device
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130288A (en) * 1981-02-03 1982-08-12 Nec Corp Nonvolatile storage device
JPS6120960B2 (en) * 1981-02-03 1986-05-24 Nippon Electric Co
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Also Published As

Publication number Publication date
JPS5918795B2 (en) 1984-04-28

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